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FlexRay Communication Controller (FlexRay)
33.5.2.37 Sync Frame ID Acceptance Filter Value Register (FR_SFIDAFVR)
Base + 0x0048
0
1
R
0
0
W
Reset
0
0
Figure 33-37. Sync Frame ID Acceptance Filter Value Register (FR_SFIDAFVR)
This register defines the sync frame acceptance filter value. For details on filtering, see
Sync frame
filtering".
Field
FVAL
Filter Value — This field defines the value for the sync frame acceptance filtering.
33.5.2.38 Sync Frame ID Acceptance Filter Mask Register (FR_SFIDAFMR)
Base + 0x004A
0
1
R
0
0
W
Reset
0
0
Figure 33-38. Sync Frame ID Acceptance Filter Mask Register (FR_SFIDAFMR)
This register defines the sync frame acceptance filter mask. For details on filtering see
Sync frame acceptance
filtering".
Field
FMSK
Filter Mask — This field defines the mask for the sync frame acceptance filtering.
33.5.2.39 Network Management Vector Registers (FR_NMVR0–FR_NMVR5)
Base + 0x004C (FR_NMVR0)
Base + 0x004E (FR_NMVR1)
Base + 0x0050 (FR_NMVR2)
Base + 0x0052 (FR_NMVR3)
Base + 0x0054 (FR_NMVR4)
Base + 0x0056 (FR_NMVR5)
0
1
2
R
W
Reset
0
0
0
Figure 33-39. Network Management Vector Registers (FR_NMVR0–FR_NMVR5)
1492
2
3
4
5
6
0
0
0
0
0
0
0
0
0
Table 33-42. FR_SFIDAFVR field description
2
3
4
5
6
0
0
0
0
0
0
0
0
0
Table 33-43. FR_SFIDAFMR field description
3
4
5
6
NMVP[15:8]
0
0
0
0
MPC5644A Microcontroller Reference Manual, Rev. 6
7
8
9
10
11
FVAL
0
0
0
0
0
Description
7
8
9
10
11
FMSK
0
0
0
0
0
Description
7
8
9
10
11
NMVP[7:0]
0
0
0
0
0
Write:
POC:config
12
13
14
15
0
0
0
0
Section 33.6.15,
Write:
POC:config
12
13
14
15
0
0
0
0
Section 33.6.15.1,
12
13
14
15
0
0
0
0
Freescale Semiconductor
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