Abort Switch Interrupt Control Register - Motorola MVME162FX Programmer's Reference Manual

ABORT Switch Interrupt Control Register

The following table describes the
the MC2 chip.
ADR/SIZ
BIT 7
NAME
OPER R
0
RESET
IL2-IL0
ICLR
IEN
INT
ABS
$FFF42040 (8 bits)
6 5 4
ABS INT IEN
R R R/W
0 PL 0 PL 0 PL
These three bits select the interrupt level for the
switch. Level 0 does not generate an
ABORT
interrupt.
Writing a logic 1 to this bit clears the abort interrupt
(i.e., the INT bit in this register). This bit is always
read as zero.
When this bit set high, the interrupt is enabled. The
interrupt is disabled when this bit is low.
When this bit is high, an interrupt is being generated
for the switch. Therefore the interrupt is
ABORT
level-sensitive to the presence of the INT bit. The
interrupt is at the level programmed in IL2-IL0.
The switch status set to a one indicates that
ABORT
the switch is pressed. When it is a zero, the
ABORT
switch is inactive.
Programming Model
switch interrupt logic in
ABORT
3 2
ICLR IL2 IL1
C R/W R/W
0 PL 0 PL 0 PL
3
1 0
IL0
R/W
0 PL
3-43