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Block Diagram
1
DRAM performance is specified in the section on the DRAM
Memory Controller in the MC2chip Programming Model in the
MVME162LX Embedded Controller Programmer's Reference Guide.
The DRAM map decoder may be programmed to accommodate
different base address(es) and sizes of mezzanine boards. The
onboard DRAM is disabled by a local bus reset and must be
programmed before the DRAM may be accessed. Refer to the
MC2chip and MCECC descriptions in the MVME162LX Embedded
Controller Programmer's Reference Guide for detailed programming
information.
Most DRAM devices require some number of access cycles before
the DRAMs are fully operational. Normally this requirement is met
by the onboard refresh circuitry and normal DRAM initialization.
However, software should insure a minimum of 10 initialization
cycles are performed to each bank of RAM.
SRAM Options
The MVME162LX provides 128KB of 32-bit-wide onboard static
RAM in a single non-interleaved architecture with onboard battery
backup. The SRAM arrays are not parity protected.
The SRAM battery backup function is provided by a Dallas
DS1210S device. The DS1210S supports primary and secondary
power sources. When the main board power fails, the DS1210S
selects the source with the higher voltage. If one source should fail,
the DS1210S switches to the redundant source. Each time the board
is powered up, the DS1210S checks power sources and if the voltage
of the backup source is less than two volts, the second memory
cycle is blocked. This allows software to provide an early warning
to avoid data loss. Because the DS1210S may block the second
access, software should do at least two accesses before relying on
the data.
The MVME162LX provides jumpers (on J14) that allow either
power source of the DS1210S to be connected to the VMEbus +5V
STDBY pin or to one cell of the onboard battery. For example, the
primary system backup source may be a battery connected to the
1-17
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