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Memory Options
The following memory options are used on the different versions of
MVME162LX Embedded Controller boards.
DRAM Options
The controller offers various DRAM options (see Table 1-1): either 1 MB
or 4 MB of parity-protected DRAM, or 4, 8, 16, or 32 MB ECC DRAM on
a mezzanine board. Parity protection can be enabled with interrupts or bus
exception when a parity error is detected. DRAM performance is specified
in the MVME162LX Embedded Controller Programmer's Reference
Guide in the section on the DRAM Memory Controller in the MCchip
Programming Model.
The DRAM map decoder can be programmed to accommodate different
base address(es) and sizes of mezzanine boards. The onboard DRAM is
disabled by a local bus reset and must be programmed before the DRAM
can be accessed. Refer to the MCchip and MCECC descriptions in the
MVME162LX Embedded Controller Programmer's Reference Guide for
detailed programming information.
Most DRAM devices require some number of access cycles before the
DRAMs are fully operational. Normally this requirement is met by the
onboard refresh circuitry and normal DRAM initialization. However,
software should insure a minimum of 10 initialization cycles are
performed to each bank of RAM.
SRAM Options
The controller provides 128 KB of 32-bit-wide onboard static RAM in a
single non-interleaved architecture with onboard battery backup.
http://www.mcg.mot.com/literature
Functional Description
1-15
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