Ddr_Vref Generation Example Circuit - Intel EP80579 Manual

9.7.3.3 DDR2 Reference Voltage, DDR_VREF
The DDR2 system memory reference voltage (DDR_VREF) is used by the DDR2-SDRAM
devices to compare the input signal levels of the data, command, and control signals.
The DDR2-SDRAM DDR_VREF must be generated as shown in
DDR_VREF from a typical resistor divider using 0.1% tolerance resistors, with a 0.01 µF
cap tied to DDR_VREF. The DDR_VREF divider resistors must be placed as close to
possible to the DIMMs. The DDR_VREF must be decoupled locally at each DIMM
connector. Finally, the DDR_VREF signal must be routed with as wide a trace as
possible.
Intel recommends at least a 20 mil wide trace with a minimum spacing of 12 mils from
other signals. For the best signal integrity, minimize this length as much as possible.
Figure 85.

DDR_VREF Generation Example Circuit

Table 47. DDR V
REF
Parameter
Nominal Trace Width
Voltage Divider
Decoupling requirements
Decoupling placement
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Intel EP80579 Integrated Processor Product Line
Platform Design Guide
133
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Intel EP80579 Integrated Processor Product Line—System Memory Interface (DIMM)
Table 47 provides the routing and component guidelines for the Vref circuit.
V1P8_DDR
49.9 Ω,
0.1%
DDR_VREF
Voltage
Circuit
49.9 Ω,
0.1%
Generation Requirements
20 mils
Place resistor divider consisting of two resistors as close as possible
to DIMMs.
0.01 µF and 0.1µF capacitors
Place one decoupling cap at each of the DIMM sockets and one
decoupling cap at the EP80579
Figure
0.01 uF 0.1 uF
Guideline
(Figure 85)
Order Number: 320068-005US
85. Generate
D
I
M
M
May 2010