Low Pin Count (Lpc) Interface; Lpc Interface - Intel EP80579 Manual

14.0

Low Pin Count (LPC) Interface

14.1

LPC Interface

The EP80579 provides a Low Pin Count (LPC) interface that is compliant with the Low
Pin Count Interface Specification, Revision 1.0. The general design of the EP80579 LPC
interface is shown in
This section provides design guidelines for interfacing properly with the LPC bus. These
guidelines help minimize signal integrity issues and maintain conformance to LPC
specifications.
The EP80579 implements all of the signals that are shown as optional; peripherals are
not a required part of the implementation.
• LAD[3:0] are shared address and data lines with device components.
• LCLK (clock) must be connected to a 33 MHz clock (EP80579 PCICLK is
recommended).
• LRESET# (reset) must be connected to EP80579's PLTRST# or PCIRST# signal.
• LFRAME# (cycle termination) is shared with FWH and the SIO.
• SERIRQ is the serialized IRQ line.
• LPCPD# (suspend status and LPC power down) is connected to the EP80579
SUS_STAT#.
• LSMI# may be connected to any of the EP80579 GPIO signals, as they may be
configured as inputs to generate an SMI#.
• Connecting the Super I/O PME# to the PME# signal is possible. A better choice is to
connect it to one of the GPIO signals, as they may be configured to generate an
SCI.
• All other signals have the same name on the EP80579 and on the LPC interface.
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Intel EP80579 Integrated Processor Product Line
Platform Design Guide
186
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Intel EP80579 Integrated Processor Product Line—Low Pin Count (LPC) Interface
Figure 123.
Figure 123 shows a general design connection to a typical LPC interface.
May 2010
Order Number: 320068-005US