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Table 52.
PCI Express Connector with LAI Connector Routing (EP80579 Receive) (Sheet
2 of 2)
Trace Length L2, L2' – to edge of logic
analyzer breakout region.
Trace Length L3, L3' – Logic analyzer
breakout region.
Trace Length L4, L4' – Logic analyzer
breakout region.
Trace Length L5, L5' – Logic analyzer
breakout region to PCI Express connector.
Trace Length LT– EP80579 pin to PCI
Express connector
AC Blocking Capacitor–AC CAP
Length Tuning Requirements
Figure 93.
PCI Express Connector With LAI Connector Routing (EP80579 Receive)
EP80579
10.1.9
Topology 3 – EP80579 to PCI Express Down Device
Table 53
and
device on the board. In this case, EP80579 is a transmitter and the PCI Express device
is a receiver. All traces must be routed on the same layer.
• L1 starts from the EP80579 breakout region to the AC blocking capacitor via.
• L2 is the main routing section that is from the AC blocking capacitor via to the PCI
Express device breakout region.
• L3 is the breakout region of the PCI Express device.
• LT is the main routing section that is from the EP80579 pin to the PCI Express
device.
®
Intel
EP80579 Integrated Processor Product Line
Platform Design Guide
145
®
Intel
EP80579 Integrated Processor Product Line—PCI Express* Interface
Parameter
Min = 0.5 in.(stripline)
Min = 0.5 in. (microstrip)
Max = 5.5 in.(stripline)
Max = 6.0 in. (microstrip)
Min = 3.5 in. (microstrip)
Max = 0.5 in. (stripline)
Max = 7.0 in. (microstrip)
Max = 0.5 in. (stripline)
Min = 2.5 in. (stripline)
Max = 7.0 in. (stripline)
LT = L1 + L2 +L3 + L4 + L5 (stripline)
LT = L1 + L2 +L3 (microstrip)
0.1 μF
Routing must remain on the same layer.
Maximum number of vias is 6 (stripline) and 4
(microstrip).
LT-LT' = ±5 mils
LT = L1 + L2 + L3 + L4 + L5
L1
L2
L3
L1'
L2'
L3'
summarize the layout routing solution space to a PCI Express
Figure 94
Routing Guidelines
LAI
Connector
L4
L5
LAI
Connector
L4'
L5'
Figure
Figure 93
Figure 93
Figure 93
Figure 93
Figure 93
Figure 93
Figure 93
PCI
Express*
Connector
May 2010
Order Number: 320068-005US
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