Address/Command With Parallel Termination Topology Diagram; A-12 Ddr2 Address/Command Signal Group Routing Guidelines - Intel EP80579 Manual

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Resistor packs are acceptable for the parallel (R
resistors, but address/command signals cannot be routed to the same resistor pack
(RPACK) used by data, data strobe, or control signals.
Figure
A-5, and
guidelines for the DDR2-SDRAM address/command signals. Do not change layers. Place
the parallel termination resistors close to the SODIMM.
Figure A-5. Address/Command With Parallel Termination Topology Diagram
EP80579
EP80579
Die
Table A-12. DDR2 Address/Command Signal Group Routing Guidelines (Sheet 1 of 2)
Signal Group
Topology
Reference Plane
Layer Assignment
Characteristic Trace Impedance (Zo)
Nominal Trace Width
Nominal Trace Spacing (e2e)
Clearance from other signals
Board Routing Guidelines
Total Trace Length (TTL) = (L
L
+ L
BREAKOUT
L
PKG
®
Intel
EP80579 Integrated Processor Product Line
Platform Design Guide
328
®
Intel
EP80579 Integrated Processor Product Line—System Memory Interface (SODIMM)
Table A-12
show the recommended topology and layout routing
EP80579
EP80579
Pin
Pin
Package
Breakout
Trace
Routing
A
B
L
L
PKG
BREAKOUT
Parameter
DDR_MA[14:0], DDR_BA[2:0], DDR_RAS#,
DDR_CAS#, DDR_WE#
Point-to-Point
Ground Referenced
Layers 3/8
40 Ω ±10%
6.5 mils
3X Trace Width
20 mils (min)
+
PKG
1.0 in - 4.5 in
+ L
)
ROUTE
BREAKIN
See the Intel
for package length information.
) address/command termination
TT
SODIMM
Breakin
Board
Routing
Routing
C
D
L
L
BREAKIN
ROUTE
Routing Guidelines for SODIMM
®
EP80579 Integrated Processor Product Line Datasheet
VTT_DDR
E
L
TERM
Figure
Figure A-5
Figure A-5
Figure A-5
May 2010
Order Number: 320068-005US

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