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Figure 78.
Example Length Matching for a Data Byte Lane
9.7.1.2
DDR2 Clock Group Signals - DDR_CLK[5:0]/DDR_CLK#[5:0]
The clock signal group includes six differential clock pairs per channel. The EP80579
generates and drives these differential clock signals. Since the EP80579 supports both
registered and unbuffered DDR2 DIMMs, three separate differential clock pairs are
routed to each DIMM connector.
Figure 79
Table 40.
Differential Clock Signal Mapping
Signal
CLK[2:0], CLK#[2:0]
CLK[5:3], CLK#[5:3]
®
Intel
EP80579 Integrated Processor Product Line
Platform Design Guide
123
®
Intel
EP80579 Integrated Processor Product Line—System Memory Interface (DIMM)
DDR_DQS[0]
DDR_DQS#[0]
DDR_DM[0]
DDR_DQ[0]
DDR_DQ[1]
DDR_DQ[2]
DDR_DQ[3]
DDR_DQ[4]
DDR_DQ[5]
DDR_DQ[6]
DDR_DQ[7]
Table 40
shows the clock interconnect between the EP80579 and the DIMMs.
Relative To
DIMM0
DIMM1
< 10 mil
< 20 mil
< 400 mil
summarizes the clock signal mapping, and
May 2010
Order Number: 320068-005US
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