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Appendix B System Memory Interface (Memory Down)
This chapter contains topologies and routing guidelines for the system memory
interface signal group of the DDR2 interface. It provides the DDR2 implementation
solution for system designs requiring memory down topologies, unbuffered or
registered, operating at 400/533/667/800 MT/s speed rates.
The EP80579 integrates a single-channel DDR2 system memory controller with a
single, 64-bit wide interface. The memory controller buffers support the SSTL_18
(1.8 V) logic switching range only. The memory controller interface is fully configurable
through a set of control registers.
The EP80579 has been validated to work with unbuffered and registered DDR2-400/
533/667/800 DIMMs. However, memory down configurations enabling unbuffered or
registered DR2-400/533/667/800 have not been fully explored. Memory down
configurations involve designs in which the memory devices are soldered onto the
motherboard. These guidelines address some of the possible challenges and best
known methods for designs using memory down configurations.
Note:
Although these guidelines are intended are to cover all aspects relating to
implementing a design with unbuffered or registered memory down DDR2- 400/533/
667/800 configurations with EP80579, it does not guarantee that every possibility has
been identified.
Note:
Unbuffered or registered memory down DDR2-400/533/667/800 design configurations
on EP80579 has NOT been validated by Intel and the data provided in these guidelines
are the results from simulation for single rank topologies only. Usage of any of the
simulation models, topology, and guidelines described in this document should be
accompanied with simulations in your own environment to ensure that your
implementation will be successful.
B.1
Terminology and Definitions
Table B-16. DDR Terminology (Sheet 1 of 2)
Acronym
Unbuffered memory
Buffered memory
Registered memory
Self-refresh
®
Intel
EP80579 Integrated Processor Product Line
Platform Design Guide
333
®
EP80579 Integrated Processor Product Line—System Memory Interface (Memory Down)
Memory that does not contain buffers or registers located on the module. The memory
controller directly communicates with the memory devices.
Memory that contains buffers on the module that re-drive signals from the memory
controller to the memory devices.
Note:
The EP80579 does not support this feature.
Memory that contains registers on the module that register and re-drives the signals
from the memory controller to the memory devices.
Memory technology that is built into the DRAM that refreshes on its own.
Description/Comment
Order Number: 320068-005US
May 2010
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