Reset Sequence - Intel EP80579 Manual

Power Management and Reset Interface—Intel
7.2.3

Reset Sequence

Figure 50
Figure 50.

Reset Sequence

EP80579
VRMPWRGD
CPU_VRM_PWR_GD
Power Applied
(from platform)
to EP80579
1
7.2.3.1 Reset Procedure
1. EP80579 receives power and drives its BSEL and V_SEL pins. IA-32 core
VRMPWRGD, and SYS_PWR_OK are not asserted. PLTRST# (platform signal) and
CPURST# (internal signal) are asserted.
2. VRMPWRGD is asserted (platform signal).
3. Reference Clock provided from platform is stabilized. Voltage regulator output is
modified to correspond to BSEL and V_SEL values.
4. CRU PLL locks.
5. SYS_PWR_OK (platform signal) == PWROK/PWRGD internal signal asserted.
6. IO and PLLs are locked to achieve stable IA-32 core Clocking.
7. IICH de-asserts PLTRST#.
8. All EP80579 blocks except the IA-32 core come out of reset.
9. IMCH de-asserts CPURST#.
®
Intel EP80579 Integrated Processor Product Line
Order Number: 320068-005US
®
EP80579 Integrated Processor Product Line
shows the reset sequence executed by EP80579 during power up.
3
Reference Clock Stable
(from clock generator)
5
4
CPUPWRGD
asserted
CRU
Clock
Stable
IICH
PWROK
PWRGD
SYS_PWR_OK
(from platform)
5
2
9
7
CPURST#
de-asserted
PLTRST#
de-asserted
10
Reset
Microcode
Execution
IICH IMCH
IMCH
6
8
CPU
All the blocks
FSB and
except the IA-32 core
Core come out of reset
Clocks
Stable
DDR2
Re-steer
Initialization
to BIOS
CPU
M-unit
Initialization
May 2010
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