Intel EP80579 Manual page 13

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Contents-Intel EP80579 Integrated Processor Product Line
146 Multi-drop Topology Diagram ...............................................................................................238
147 Chip Select Point-to-Point Topology Diagram......................................................................239
148 Address Signals Star Topology Diagram .............................................................................241
149 Data, and Control Signals Star Topology Diagram ..............................................................242
150 Address, Data, and Control Signals Mezzanine Star Topology Diagram .............................244
151 TDM to SLIC/CODEC Interface Example.............................................................................248
152 SSP to Serial Flash Interface Example ................................................................................252
153 Termination After Last Receiver...........................................................................................260
154 Termination Prior to Last Receiver .......................................................................................260
155 TDI-TDO Routing .................................................................................................................261
156 BPM5 and BPM3_in Platform Circuit ...................................................................................262
157 XDP Connector System Keep-Out Diagram ........................................................................266
A-1 DDR2 Interfaced System Interconnect.................................................................................320
A-2 Data/Mask/Strobe Signal Routing Topology Diagram..........................................................321
A-3 DDR2 Point-to-Point Clock Routing Diagram.......................................................................323
A-4 DDR2 Control Signals- Implementation ...............................................................................325
A-5 Address/Command With Parallel Termination Topology Diagram.......................................327
A-6 DDR_SLWCRES, DDR_RCOMPX, DDV_CRES, & DDR_CRES0 Routing Topology ........329
A-7 DDR_CRES1 and DDR_CRES2 Signal Connections..........................................................329
A-8 DDR_VREF Generation Example Circuit.............................................................................330
B-9 DDR2 Clock Signal Routing Topology (One Clock for Three Devices)................................339
B-10 DDR2 Data/DM/ECC Byte Lane Topology...........................................................................341
B-11 DDR2 Data Strobe Routing (DQS/DQS#) Topology (One Strobe per Byte Lane)...............341
B-12 DDR2 Address, Command and Control Signal Routing Topology.......................................343
B-13 DDR_SLWCRES, DDR_RCOMPX, DDV_CRES, & DDR_CRES0 Routing Topology ........345
B-14 DDR_CRES1 and DDR_CRES2 Signal Connections..........................................................346
Tables
1 Reference Documents ...........................................................................................................20
2 Acronyms and Terminology ...................................................................................................21
3 EP80579 Feature List.............................................................................................................25
4 Development Board Feature List............................................................................................28
5 EP80579 External Clock Requirements .................................................................................30
6 Assumptions for System Placement Example........................................................................32
7 Development Board Summary ..............................................................................................36
8 Terminology............................................................................................................................64
9 Power Supply Pins .................................................................................................................65
10 Power and Ground Planes .....................................................................................................66
11 Development Board Power Delivery Voltage Definitions .......................................................69
12 IA-32 core Frequency and Power Select (BSEL/V_SEL).......................................................70
13 Analog and Bandgap Filter Components ...............................................................................79
14 Types of Reset and Wake-up from Power Saving States ......................................................84
15 Three Basic System Power States.........................................................................................88
16 CK410 Clock Groups..............................................................................................................92
17 Platform System Clock Reference .........................................................................................92
18 HOST_CLK Routing Guidelines .............................................................................................95
19 100 MHz SRC/SRC# Clock Routing Guidelines for Down Devices(Except PCI-E) ...............97
20 100 MHz SRC/SRC# Clock Routing Guidelines for PCI Express Slot/Component ...............98
21 CLK33 Routing Guidelines to EP80579, FWH, and LPC Down Devices .............................100
22 CLK33 Routing Guidelines for Two Down Devices ..............................................................101
May 2010
Order Number: 320068-005US
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Intel EP80579 Integrated Processor Product Line
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