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PCI Express* Interface—Intel
Table 50.
PCI Express Connector Routing (EP80579 Receive)
Signal Group
Reference Plane
Layer Assignment
Characteristic Trace Impedance (Zo)
Nominal Trace Width
Nominal Trace Spacing within a pair from
edge to edge
Nominal Trace Spacing from edge of one
differential pair to edge of another
differential pair
Trace Length L1, L1'– EP80579 Breakout
region
Trace Length L2, L2' – PCI Express
connector
Trace Length LT– EP80579 pin to PCI
Express connector
Length Tuning Requirements
Figure 91.
PCI Express Connector Routing (EP80579 Receive)
10.1.8
Topology 2 – EP80579 to PCI Express Connector
with Logic Analyzer Connector
Table 51
connector on the board with a logic analyzer connector. In this case, EP80579 is a
transmitter and the PCI Express connector is a receiver. All traces must be routed on
the same layer.
• L1 starts from the EP80579 breakout region to the AC blocking capacitor via.
• L2 is the main routing section that is from the AC blocking capacitor via to the logic
analyzer connector.
®
Intel
EP80579 Integrated Processor Product Line
Order Number: 320068-005US
®
EP80579 Integrated Processor Product Line
Parameter
EP80579
and
summarize the layout routing solution space to a PCI Express
Figure 92
Routing Guidelines
PEA0_Rn[7:0], PEA0_Rp[7:0]
Ground Referenced
Layers 3 or 8 (stripline)
Layers 1 or 10 (microstrip)
90 Ω ±10% (Differential)
4.5 mils (stripline)
4.75 mils (microstrip)
5.5 mils (stripline)
5.25 mils (microstrip)
The greater of:
• 18 mils or 3x dielectric thickness (stripline)
• 20 mils or 5x dielectric thickness
(microstrip)
Min = 0.5 in.
Max = 2.5 in.
Min = 4.5 in.
Max = 15.5 in.(stripline)
Max = 15.0 in. (microstrip)
LT = L1 + L2
Routing must remain on the same layer.
Maximum number of vias is 4.
LT-LT' = ±5 mils
LT = L1 + L2
L1
Express*
L1'
Connector
Figure
Figure 87
Figure 88
Figure 87
Figure 88
Figure 87
Figure 88
Figure 91
Figure 91
Figure 91
Figure 91
PCI
May 2010
142
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