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PCI Express* Interface—Intel
Table 53.
PCI Express Down Device Routing (EP80579 Transmit)
Signal Group
Reference Plane
Layer Assignment
Characteristic Trace Impedance (Zo)
Nominal Trace Width
Nominal Trace Spacing within a pair from
edge to edge
Nominal Trace Spacing from edge of one
differential pair to edge of another
differential pair
Trace Length L1, L1'– EP80579 Breakout
region and to AC CAP
Trace Length L2, L2' – AC CAP to PCI
Express Device breakout region
Trace Length L3, L3'– Express Device
breakout region
Trace Length LT– EP80579 pin to PCI
Express Device
AC Blocking Capacitor–AC CAP
Length Tuning Requirements
Figure 94.
PCI Express Down Device Routing (EP80579 Transmit)
Table 54
board device. In this case, EP80579 is a receiver and the PCI Express device is a
transmitter. LT must be routed on the same layer and the signals must reference one
continuous plane.
• L1 is the EP80579 breakout region.
®
Intel
EP80579 Integrated Processor Product Line
Order Number: 320068-005US
®
EP80579 Integrated Processor Product Line
Parameter
L1
EP80579
L1'
and
summarize the layout routing solution space to a PCI Express on
Figure 95
Routing Guidelines
PEA0_Tn[7:0], PEA0_Tp[7:0]
Ground Referenced
Layers 3 or 8 (stripline)
Layers 1 or 10 (microstrip)
90 Ω ±10% (Differential)
4.5 mils (stripline)
4.75 mils (microstrip)
5.5 mils (stripline)
5.25 mils (microstrip)
The greater of:
• 18 mils or 3x dielectric thickness (stripline)
• 20 mils or 3x dielectric thickness
(microstrip)
Min = 0.75 in.
Max = 2.5 in.
Min = 4.0 in (stripline)
Min = 2.5 in (microstrip)
Max = 14.5 in. (stripline)
Max = 13.0 in. (microstrip)
Min = 0.75 in.
Max = 2.0 in.
LT = L1 + L2 + L3
0.1 μF
Routing must remain on the same layer.
Maximum number of vias is 4.
LT-LT' = ±5 mils
LT = L1 + L2 + L3
L2
L3
AC CAP
L2'
L3'
AC CAP
Figure
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Figure 87
Figure 88
Figure 87
Figure 88
Figure 87
Figure 88
Figure 94
Figure 94
Figure 94
Figure 94
Figure 94
Figure 94
PCI
Express*
Device
May 2010
146
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