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The resistive mechanism on those I/O pads references external resistors that the user
provides to optimize the signal impedance termination. Thus the output driver
impedance can be tuned specifically to the application PCB characteristics for nominal
signal transfer into the transmission lines formed by the PCB traces. The RCOMP design
is nominally set to operate at 50 ohm, but the user is free to set the impedance in the
range 45 ohm to 55 ohm.
Two RCOMP pins (GbE RCOMPP and GbE RCOMPN) are provided to establish the GbE
output driver impedance, one to control the drive high strength and one to control the
drive low strength. These RCOMP outputs drive into external resistors. For the
Development Board, the GbE RCOMPP is connected via a 50 ohm resistor to ground,
while GbE RCOMPN is connected through a 50 ohm resistor to the GbE auxiliary power
supply. The drivers form a resistor divider and the voltages developed in these dividers
are compared to a reference voltage. The RCOMP state machine independently adjusts
the strength of the drivers making them stronger or weaker until the comparator
signals that the voltage is greater than or less than the reference. The state machine
will continue making adjustments causing the comparators to oscillate between two
strength settings just above and just below the comparator trip point. Logic in the
RCOMP state machine recognizes when this "dithering" between the two values has
begun and holds the strength output for the GbE outputs fixed at one of the two
settings. Note this algorithm is independently and concurrently applied to the drive
high strength and to the drive low strength.
The GbE RCOMP controller starts operation when the GBE_AUX_PWR_GOOD input is
asserted. This condition indicates the power supplies are stable; the condition also
indicates that the GBE_REFCLK input is being driven with a 125 MHz clock. The
GBE_REFCLK input is divided by either 4 or 16 and then used to drive the RCOMP state
machine. Software accessible registers that provide options to monitor/overwrite
internal bias and comparator output are also present.
19.10
Crosstalk Considerations
Noise due to crosstalk must be carefully controlled to a minimum. Crosstalk is the key
cause of timing skews and is the largest part of the tRMATCH skew parameter.
tRMATCH is the sum of the trace length mismatch between GbE Clock and Data signals.
To meet this requirement on the board, the length of each data trace is either equal to
or up to 0.5 inches shorter than the clock trace. Maintaining at least 100 mils of spacing
should minimize noise due to crosstalk from non-GbE signals.
19.11
Pull-up Termination
For the Development Board, signal pull-up termination is implemented at the receiver
side of the interface to achieve acceptable signal integrity by controlling signal
reflection, overshoot/undershoot, and ringback.
recommended pull-up termination value at the receiver endpoint. The system designer
should ensure through simulations or other techniques that the pull-up termination is
required and fulfils their specific LAN interface signal integrity requirements.
19.12
General Gigabit Ethernet Design Guidelines
The platform GbE Connect Interface signals must be carefully routed on the
motherboard to meet the timing and signal quality requirements of the interface
specification. Some general guidelines appear below. The board designer should
simulate the board routing to verify that the specifications are met for flight times and
skews due to trace mismatch and crosstalk.
Use the following general routing and placement guidelines when laying out a new
design (see
®
Intel
EP80579 Integrated Processor Product Line
Platform Design Guide
227
®
Intel
EP80579 Integrated Processor Product Line—Gigabit Ethernet (GbE) Interface
Figure 139
and
Figure
140):
Table 85
and
Table 86
provide the
Order Number: 320068-005US
May 2010
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