Intel EP80579 Manual page 273

Integrated processor product line
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®
Layout Checklist—Intel
EP80579 Integrated Processor Product Line
Table 97.
Layout Checklist (Sheet 5 of 13)
Signal Name
PEA0_Rp[7:0],
PEA0_Rn[7:0]
PEA_CLKp,
PEA_CLKn
PEA_ICOMPI,
PEA_ICOMPO,
PEA_RCOMPO
PE_HPINTR#
Real Time Clock (RTC)
RTCX1,
RTCX2
RTEST#
GPIO[1:0]
GP2_PIRQE#
®
Intel
EP80579 Integrated Processor Product Line
Order Number: 320068-005US
Trace Geometry and
Impedance
Ω
Zdiff = 90
+/- 10%
Trace Width:
Brakeout Trace Width 4 mils
Microstrip: 4.75 mils
Stripline: 4.5 mils (L3/L8)
Airgap Spacing:
Brakeout spacing Min=4mils
Microstrip: 5.25 mils
Stripline: 5.5 mils
Spacing between Pairs, the
greater of the two
Microstrip: 20 mils or 3X
dielectric thickness.
Stripline: 18 mils or 3X dielectric
thickness.
Ω
Zdiff = 100
+/- 10%
Trace Width:
Brakeout Trace Width 4 mils
Microstrip: 4 mils
Stripline: 3.75 mils(L3/L8)
Stripline: 4.25 mils(L5/L6)
Airgap Spacing:
Brakeout spacing Min=4mils
PEA_CLKp to PEA_CLKn
Microstrip: 6 mils
Stripline: 9 mils
Spacing to other signals 20 mils
Serpentine Spacing 20 mils
Ω
Zo = 50
+/- 10%
Ω
Zo = 50
+/- 10%
Integrated I/O Controller Hub (IICH) Interface
Ω
Zo = 50
+/- 10%
Trace Width:
Microstrip: 5.5 mils
Airgap Spacing
Microstrip: 9 mils
Spacing to other signals 2 X
Ω
Zo = 50
+/- 10%
General Purpose I/O (GPIO) and Interrupts Interface
Ω
Zo = 50
+/- 10%
Ω
Zo = 50
+/- 10%
Length Requirements
Inter-pair length
See
matching: +/-5 mils.
– EP80579 to PCI Express
Connector".
Within a link, the lane-to-
lane skew should meet
Maximum number of vias per
the PCIe receive skew
signal is 4.
(rx-skew) specification.
See
Clock)
Inter-pair length
matching: +/- 5 mils
Maximum number of vias per
signal is 4.
See
Crystal".
Avoiding routing of adjacent PCI
signals close to RTCX1 and
RTCX2.
Use of a ground guard plane is
Routing Length LT:
highly recommended.
Max = 1.2 in.
Put GND plane underneath
Crystal components.
Minimize capacitance between
RTCX1 and RTCX2.
Don't route switching signals
under the external components
(unless on other side of board).
Comments
Section 10.1.7, "Topology 1
Section 8.2.2, "CLK100 (SRC
Group".
Section 15.1.1, "RTC
May 2010
273

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