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Synchronous Peripheral Interface (SPI)—Intel
16.2.1
SPI Routing Guidelines
Figure 133. SPI Topology (System BIOS Only)
EP80579
SPI_MOSI
SPI_MOSO
SPI_CS0#
SPI_CLK
Table 73.
SPI Single Flash Device Routing Summary
Signal Name
Impedance
SPI_MOSI
SPI_MISO
50Ω ±10%
SPI_CS0#
SPI_CLK
SPI_MOSI
SPI_MISO
50Ω ±10%
SPI_CS0#
SPI_CLK
1. W represents width of signal; S represents spacing to any other signal.
2. R1 = 15Ω and should be placed 0.1-1" from the EP80579.
3. R2 = 15Ω and should be placed 0.1-1" from the serial flash device.
16.2.2
Boot BIOS Selection
GPIO[17] and GPIO[33] have internal 50 KΩ pull-ups which set the default bootup to
the FWH. The SPI boot option is implemented by strapping GPIO[17] and GPIO[33] to
ground (GND) through 1KΩ pull-down resistors. See
®
Intel
EP80579 Integrated Processor Product Line
Order Number: 320068-005US
®
EP80579 Integrated Processor Product Line
R1
L2
L1
L1
R1
L1
L2
R1
L2
L1
Width (W) /
Layer
Spacing (S)
L1 = 1"-11"
W = 4.5 mils
Microstrip
L2 = 0.1"-0.5"
S = 7 mils
L3 = 0.1"-0.5"
L1 = 1"-11"
W = 3.75mils
Stripline
L2 = 0.1"-0.5"
S = 7 mils
L3 = 0.1"-0.5"
Serial Flash
Serial In
R2
L3
Serial Out
Chip Select
Clock
Length
Breakout
W = 4 mils
S = 4 mils
L = <1"
W = 4 mils
S = 4 mils
L = <1"
Table 74
for strapping options.
Figure
Notes
1
2
3
Figure 133
,
,
Figure 133
1,2,3
May 2010
200
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