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Table 49.
PCI Express Connector Routing (EP80579 Transmit)
Signal Group
Reference Plane
Layer Assignment
Characteristic Trace Impedance (Zo)
Nominal Trace Width
Nominal Trace Spacing within a pair from
edge to edge
Nominal Trace Spacing from edge of one
differential pair to edge of another
differential pair
Trace Length L1, L1'– EP80579 Breakout
region and to AC CAP
Trace Length L2, L2' + L3, L3'– AC CAP to
PCI Express connector
Trace Length LT– EP80579 pin to PCI
Express connector
AC Capacitor–AC CAP
Length Tuning Requirements
Figure 90.
PCI Express Connector Routing (EP80579 Transmit)
EP80579
Table 50
and
connector. In this case, EP80579 is a receiver and the PCI Express connector is a
transmitter. LT must be routed on the same layer.
• L1 is the EP80579 breakout region.
• L2 starts from the edge of the EP80579 breakout region to the PCI Express
connector.
• LT is the main routing section that is from the EP80579 pin to the connector.
®
Intel
EP80579 Integrated Processor Product Line
Platform Design Guide
141
®
Intel
EP80579 Integrated Processor Product Line—PCI Express* Interface
Parameter
PEA0_Tn[7:0], PEA0_Tp[7:0]
Ground Referenced
Layers 3 or 8 (stripline)
Layers 1 or 10 (microstrip)
90 Ω ±10% (Differential)
4.5 mils (stripline)
4.75 mils (microstrip)
5.5 mils (stripline)
5.25 mils (microstrip)
The greater of:
Min = 0.5 in.
Max = 2.5 in.
Min = 4.5 in.
Max = 15.5 in.(stripline)
Max = 15.0 in. (microstrip)
LT = L1 + L2 + L3
0.1 μF
Routing must remain on the same layer.
Maximum number of vias is 4.
LT-LT' = ±5 mils
LT = L1 + L2 + L3
L1
AC CAP
L1'
AC CAP
Figure 91
summarize the layout routing solution space to a PCI Express
Routing Guidelines
• 18 mils or 3x dielectric thickness (stripline)
• 20 mils or 3x dielectric thickness
(microstrip)
L3
L2
L3'
L2'
Figure
-
-
-
-
Figure 87
Figure 88
Figure 87
Figure 88
Figure 87
Figure 88
Figure 90
Figure 90
Figure 90
Figure 90
Figure 90
PCI
Express*
Connector
May 2010
Order Number: 320068-005US
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