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Debug Port Design Guide—Intel
26.3.3.8
XDP_Present
This optional steady-state output from the run-control hardware indicates the presence
of an ITP-XDP-style tool at the debug port. To use this tool, the target system must
provide a pull-up termination of 1k to 10k ohm to this signal. Termination voltage for
this signal can be to any voltage that is compatible with the receiver chosen by the
platform design.
When the ITP-XDP tool is present, the ITP-XDP tool will short this pin to ground.
2
26.3.4
I
C (SDA/SCL) Routing Guidelines
2
The I
C interface from the ITP-XDP includes two pins – SDA and SCL. Route the debug-
port SDA pin to the SDA signal of the I
to the SCL signal of the I
and cannot be slave addressed. The I
multiple-master I
required for validation and debug. The ITP-XDP conforms to the multi-master rules of
2
the I
C bus. The debug port has no additional requirements for termination on these
signals beyond the I
Bus protocols.
There are no additional requirements for termination on these signals beyond the I
specifications.
26.3.5
Power
26.3.5.1
VCC_OBS Pins
The VCC_OBS_AB and VCC_OBS_CD pins are used by the ITP-XDP hardware to provide
termination voltage to the OBS interface. Connect VCC_OBS_AB and VCC_OBS_CD to
the voltage listed in the system-connection table. Decoupling capacitors are not
required for these signals.
Each of these pins draws ~200mA of current.
26.3.5.2
Ground
All XDP ground signals must be tied directly to the system ground with little to no trace
from the debug port.
26.4
System Connection
The XDP connector placed on the target system is a Samtec* 60-pin BSH-030-01 series
connector. Specific plating types, locking clips, and alignment pins versions of this
connector can be obtained from Samtec*.
connector.
Table 95.
XDP To EP80579 Signal Connections (Sheet 1 of 2)
Pin
XDP Signal Name
1
GND
3
OBSFN_A0
5
OBSFN_A1
®
Intel
EP80579 Integrated Processor Product Line
Order Number: 320068-005US
®
EP80579 Integrated Processor Product Line
2
C on the system. The I
2
C bus within the target system that provides access to the hooks
2
C specifications. The I
Target
I/O
Device
Signal
GND
NA
BPM5_PREQ
I/O
EP80579
_IN
BPM4_PRDY
I/O
EP80579
_OUT
2
C on the system. Route the debug port SCL pin
2
C ITP-XDP interface is master only
2
C ITP-XDP master can be connected to any
2
C ITP-XDP is compatible with I
Table 95
documents the pinout for ITP-XDP
XDP Signal
Pin
Name
2
GND
GND
4
OBSFN_C0
Open
6
OBSFN_C1
Open
2
C and SM
2
C
Target
I/O
Device
Signal
NA
System
NA
NA
May 2010
265
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