Intel EP80579 Manual page 271

®
Layout Checklist—Intel EP80579 Integrated Processor Product Line
Table 97. Layout Checklist (Sheet 3 of 13)
Signal Name
DDR_A[14:0],
DDR_BA[2:0],
DDR_RAS#,
DDR_CAS#,
DDR_WE#
DDR_CS[1:0]#,
DDR_CKE[1:0],
DDR_ODT[1:0]
®
Intel EP80579 Integrated Processor Product Line
Order Number: 320068-005US
Trace Geometry and
Impedance
Zo = 40 Ω +/- 10% single ended
Trace Width:
Brakeout Trace Width 4 mils
Stripline: 6.5 mils(L3/L8)
Airgap Spacing:
Brakeout spacing Min=4 mils
Between group signals
Min=15mils
To any other signals Min=20mils
Ω
Zo = 40 +/- 10% single ended
Trace Width:
Brakeout Trace Width 4 mils
Stripline: 6.5 mils(L3/L8)
Airgap Spacing:
Brakeout spacing Min=4mils
Between group signals
Min=15mils
To any other signals Min=20mils
Length Requirements
See
EP80579 to First DIMM
System
2.0 in to 4.0 in Max
Topology Daisy Chain
Reference Plane:
First to Second DIMM
Ground and Power reference
Max=0.8 in
plane
Route groups of signals on the
Total Trace Length (TTL)
same layer from EP80579 to the
2.0 in - 6.0 in
farthest DIMM.
Termination Trace Length
No vias, except were required to
Max = 0.5 in. Skew
breakout.
between Termination
Trace Length should not
Place Ccomp caps as close as
exceed 200 mils.
possible to the DIMM
Skew: Match all group
signals within 20 mils.
The shortest signal of the
group must not exceed
the longest signal of the
group by 20 mils. This
requirement is for the
complete length from
EP80579 to the farthest
DIMM connector.
See
EP80579 to First DIMM
System
2.0 in to 4.0 in Max
Topology Daisy Chain
Reference Plane:
First to Second DIMM
Ground and Power reference
Max=0.8 in
plane
Route groups of signals on the
Total Trace Length (TTL)
same layer from EP80579 to the
2.0 in - 6.0 in
farthest DIMM.
No vias, except were required to
breakout.
Termination Trace Length
Max = 0.5 in. Skew
between Termination
Trace Length should not
exceed 200 mils.
Skew: Match all group
signals within 20 mils.
The shortest signal of the
group must not exceed
the longest signal of the
group by 20 mils. This
requirement is for the
complete length from
EP80579 to the farthest
DIMM connector.
Comments
Section 9.7, "DDR2 Interface
Interconnect".
Section 9.7, "DDR2 Interface
Interconnect".
May 2010
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