Layout Checklist - Intel EP80579 Manual

®
Layout Checklist—Intel EP80579 Integrated Processor Product Line
27.2

Layout Checklist

s
Table 97. Layout Checklist (Sheet 1 of 13)
Signal Name
Global Clock Unit (CRU)
CLKP100/CLKN100
or
BCLKP/BCLKN
Thermal Diode
THERMDA
THERMDC
Sideband Miscellaneous Signals
CPUSLP_OUT#
INIT33V_OUT#
NMI
SMI_OUT#
STPCLK_OUT#
RCIN#
A20GATE
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Intel EP80579 Integrated Processor Product Line
Order Number: 320068-005US
Trace Geometry and
Impedance
IA-32 core Interface
Ω
Zdiff = 100 +/- 10%
Trace Width – W
Brakeout Trace Width 4 mils
Microstrip: 4 mils
Stripline: 3.75 mils(L3/L8)
Stripline: 4.25 mils(L5/L6)
Brakeout Trace Width 4 mils
Airgap Spacing:
Brakeout spacing Min=4mils
Microstrip: 6 mils
Stripline: 9 mils
Spacing between Pairs 20mils
Spacing to other signals 20 mils
Serpentine Spacing 20 mils
Recommended Trace Width:
Trace width = 10 mils.
Spacing to other signals 1 X
trace width.
Ω
Zo = 50 +/- 10%
Spacing to other signals 3 X
trace width.
Ω
Zo = 50 +/- 10%
Spacing to other signals 3 X
trace width.
Ω
Zo = 50 +/- 10%
Spacing to other signals 3 X
trace width.
Ω
Zo = 50 +/- 10%
Spacing to other signals 3 X
trace width.
Ω
Zo = 50 +/- 10%
Spacing to other signals 3 X
trace width.
Ω
Zo = 50 +/- 10%
Spacing to other signals 3 X
trace width.
Ω
Zo = 50 +/- 10%
Spacing to other signals 3 X
trace width.
Length Requirements
Routing Length LT:
Min = 1 in.
Max = 10 in. See
Topology".
Inter-Pair length
matching: +/- 5 mils
Remote sensor should place as
close as possible to THERMDA
and THERMDC, approximately 4
to 8" away from the noise
sources.
Route the THERMDA and
THERMDC lines parallel and close
together with ground guards
enclosing them.
Comments
Section 8.2.1.1, "HOST_CLK
May 2010
269