Ddr2 Control Signals- Implementation; Ddr2 Control Signal Group Routing Guidelines - Intel EP80579 Manual

Figure 81.

DDR2 Control Signals- Implementation

EP80579
CKE0
CS0#
ODT0
CKE1
CS1#
ODT1
Table 42. DDR2 Control Signal Group Routing Guidelines (Sheet 1 of 2)
Signal Group
Topology
Reference Plane
Layer Assignment
Characteristic Trace Impedance (Zo)
Nominal Trace Width
Nominal Trace Spacing (e2e)
®
Intel EP80579 Integrated Processor Product Line
Platform Design Guide
127
®
Intel EP80579 Integrated Processor Product Line—System Memory Interface (DIMM)
Board
Breakout
Package
Routing
Routing
Trace
A
B
L
L
BREAK
PKG
Routing Guidelines for 2-DIMM Solution with
Parameter
Control Signals (CS#/ODT/CKE)
Daisy Chain
Ground Referenced
Layers 3/8
40 Ω ±10%
6.5 mils
15 mils
DIMM 0
DIMM 1
DIMM2DIMM
Routing
C
D
L
L
ROUTE
D2D
ODT
VTT_DDR
VTT_DDR
E
L
TERM
Figure
Figure 76
Figure 81
Figure 81
Figure 81
May 2010
Order Number: 320068-005US