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®
®
Intel
Pentium
M Processor and Intel
®
Intel
82870P2 (Intel P64H2)
Figure 96.
Tri-State Buffer Circuit Example
It is also possible to accomplish this strapping requirement using a 2:1 multiplexer. The PWROK
signal may be used to enable the tri-state buffer. The decision is left up to the individual designer
on which method to use. See
Figure 97.
MUX Circuit Example
This signal could be
pulled up to VCC_3.3
depending on the
strapping need.
PCIXCAP1 / PCIXCAP2
8.2.7.6
Hot-Plug Multiplexed Signals in Single-Slot Parallel Mode
The Hot-Plug signals that connect to the controller are shown in
column refers to the name of the slot pin when in single-slot mode. The 'Bus A' and
'Bus B' columns represent the corresponding Intel
Table 76.
Single-Slot Parallel Mode Hot-Plug Signal Table
Signal
HxSWITCHA
HxFAULTA#
HxPRSNT2A#
NOTES:
1. HPx_SLOT [N] are pull-ups/pull-downs. When in dual-slot parallel mode, the external logic that decodes
the three-state value of PCIXCAP from the card must actively drive these signals to either logic 1 or logic 0
to overcome the value of the pull-up/pull-down, and must be tri-stated during reset and while the card is not
connected to avoid damaging the slot count value.
2. The Intel
set up for single-slot parallel mode so that LEDs are in the appropriate state (off), and the Q-switches
remain disconnected. Note that the placement of the signals should be such that the value driven by the
Intel P64H2 in dual-slot parallel mode is the same value it would have driven when in serial mode.
3. In both parallel modes, the BUSEN# and CLKEN# signals become active low instead of active high as they
are during serial mode.
138
®
E7501 Chipset Platform
PC IXCA P x
Input
Decoded P CIXCA P
Signal from PC I S LO T
Figure 97
1 k Ω
2:1 Multiplexer
S 1
S 2
PWROK
Type
Bus A
I
PAIRQ15
I
PAIRQ14
I
PAIRQ13
®
P64H2 must drive this signal to its corresponding state shown in
Enabled by PW ROK #
EN B
Ω
1 k
for an example of the optional multiplexer circuit.
D
(PCIXCAP1 / PCIXCAP2) or HPxSLOT Strap
VCC_3.3
8.2 kΩ
C ENB
®
P64H2 pins.
Multiplexed With
Ball #
F4
PBIRQ15
E4
PBIRQ14
F5
PBIRQ13
Truth Table
C (PWROK)
D
0
HPxSLOT Strap
1
PCIXCAP1 / PCIXCAP2
Table
76. In
Table 76
the 'Signal'
Bus B
Ball #
F1
E1
D1
Table 77
in case the system is
Design Guide
Note
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