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Platform System Clock—Intel
Figure 59.
Topology for CLK33 to Down Devices
Table 21.
CLK33 Routing Guidelines to EP80579, FWH, and LPC Down Devices
Clock Group
Topology
Reference Plane
Characteristic Trace Impedance (Z
Trace Width (W)
Trace Spacing (S1)
EP80579, FWH, and other LPC down devices
Trace Length (L1)
EP80579 (L2)
FWH, Port80, TPM, SIO Trace Length (L2)
Resistor
Note:
1.
Ground referencing is preferred. However, CLK33 can be routed referenced to other planes if the
plane is contiguous from source to destination
2.
Trace width is stackup dependent. Routing guidelines are for the width is 4.5 mils with 6.25 mil
spacing on layers 3 & 8.
3.
Length Z = L1 + L2, from
4.
The value of Rs may need to be increased for shorter trace lengths to minimize overshoot /
undershoot effects.
Figure 60.
Trace Spacing for CLK33 (PCICLK) Clock
®
Intel
EP80579 Integrated Processor Product Line
Order Number: 320068-005US
®
EP80579 Integrated Processor Product Line
L1
Clock
Driver
Parameter
)
0
Figure
58.
S1
L2
Rs
Routing Guidelines
CLK33: 33 MHz clocks - Port80,
FWH, LPC, TPM, SIO,
ICH_33MHz_CLK,
ITP_PCI_CLK_33MHz
Point-to-point
Ground referenced (contiguous
over entire length)
55 Ω ± 10%
microstrip: 4.5 mils
stripline: 4.75 mils
20 mils
0.5" max
L2 = Z = 2" to 20"
L2 = [Z + (0" to 6")] = 20" max
Rs = 43 Ω ±5%
W
PCICLK
S1
h
Ground Plane
EP80579 or Down
Devices
Illustrations
Notes
Figure 59
1
Figure 60
2
Figure 60
Figure 59
Figure 59
3,
4
Figure 59
3,
4
Figure 59
4
May 2010
100
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