Lpc Layout; General Routing And Placement; Lpc Interface Routing And Topology; Lpc Interface Diagram - Intel EP80579 Manual

Low Pin Count (LPC) Interface—Intel
Figure 123. LPC Interface Diagram
14.2

LPC Layout

14.2.1

General Routing and Placement

Use the following general routing and placement guidelines when laying out a new
design:
• LPC signals should be ground referenced.
• Route all traces using microstrip or stripline over continuous planes (Vcc or GND)
with no interruptions. Avoid crossing over anti-etch if at all possible. Any
discontinuity or split in the ground plane may cause signal reflections and should be
avoided.
• Route LPC signals using a minimum of vias and corners. This reduces reflections
and impedance changes.
• No 90-degree bends or stubs.
14.2.2

LPC Interface Routing and Topology

This section provides guidelines for topology routing. The Development Board provides
four basic component devices connected to the EP80579's LPC interface. These devices
include:
• port 80
• Firmware Hub
• Trusted Platform Module
• Super IO
Figure 124
®
Intel EP80579 Integrated Processor Product Line
Order Number: 320068-005US
®
EP80579 Integrated Processor Product Line
PCICLK or CLK 33 MHz
EP80579
LAD[3:0]
LFRAME#
LDRQ#
(optional)
LPCPD#
SUS_STAT#
(optional)
SERIRQ
PLTRST#
LRESET#
or
PCIRST#
SMBCLK/DATA
(optional)
PME#
(optional)
LSMI#
GPI
(optional)
provides a block diagram:
LPC Interface
May 2010
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