Intel EP80579 Manual page 7

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Contents-Intel EP80579 Integrated Processor Product Line
13.1.2 General Design Considerations ...........................................................................179
13.1.3 High Power/Low Power Mixed Architecture.........................................................179
13.1.4 Calculating the Physical Segment Pull-Up Resistor ............................................180
13.2 Enabled System Management Features (Optional)..........................................................180
13.3 Enabled System Management Vendors (Optional) ..........................................................181
13.4 Development Board System Management Implementation .............................................182
13.4.1 SIO Implementation .............................................................................................184
14.0 Low Pin Count (LPC) Interface ....................................................................................................186
14.1 LPC Interface....................................................................................................................186
14.2 LPC Layout .......................................................................................................................187
14.2.1 General Routing and Placement..........................................................................187
14.2.2 LPC Interface Routing and Topology...................................................................187
14.2.3 Clock Signals -- CLK33........................................................................................189
14.3 Trusted Platform Module (TPM) Guidelines .....................................................................189
14.3.1 TPM Design Considerations ................................................................................189
14.3.2 TPM Design Considerations ................................................................................189
14.3.3 Motherboard Placement Consideration ...............................................................190
14.4 Firmware Hub (FWH) Guidelines......................................................................................191
14.4.1 FWH and Flash BIOS Vendors ............................................................................191
14.4.2 FWH Decoupling..................................................................................................191
14.4.3 FWH INIT# Voltage Compatibility ........................................................................191
14.4.4 FWH VPP Design Guidelines (Optional)..............................................................191
15.0 Real Time Clock (RTC) Interface ................................................................................................193
15.1 RTC Interface ...................................................................................................................193
15.1.1 RTC Crystal .........................................................................................................193
15.1.2 External Capacitors .............................................................................................194
15.1.3 RTC Layout Considerations.................................................................................195
15.1.4 RTC External Battery Connection........................................................................196
15.1.5 Internal only RTC External RTEST# Circuit.........................................................197
15.1.6 SUSCLK ..............................................................................................................197
15.1.7 RTC Well Input Strap Requirements....................................................................198
16.0 Synchronous Peripheral Interface (SPI) ......................................................................................199
16.1 Terminating Unused SPI Port ...........................................................................................199
16.2 SPI Interface General Routing Guidelines ........................................................................199
16.2.1 SPI Routing Guidelines........................................................................................200
16.2.2 Boot BIOS Selection ............................................................................................200
16.2.3 Serial Flash Vendors ...........................................................................................201
17.0 General Purpose I/O (GPIO) and Interrupt Interface ...................................................................202
17.1 GPIO Signals ....................................................................................................................202
17.1.1 Development Board GPIO Usage........................................................................203
17.2 Interrupts...........................................................................................................................204
18.0 Serial Interface Unit (SIU/UART) .................................................................................................206
18.1 SIU (UART) Interface........................................................................................................206
18.1.1 SIU Interface Signals ...........................................................................................206
18.1.2 SIU Interface Interconnect ...................................................................................207
May 2010
Order Number: 320068-005US
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Intel EP80579 Integrated Processor Product Line
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