Ddr2 Point-To-Point Clock Routing Diagram; Clock Signal Group Routing Guidelines - Intel EP80579 Manual

Figure 80.

DDR2 Point-to-Point Clock Routing Diagram

Table 41. Clock Signal Group Routing Guidelines (Sheet 1 of 2)
Signal Group
Topology
Reference Plane
Layer Assignment
Characteristic Trace Impedance (Zo)
Nominal Trace Width
Inter-pair Trace Spacing(e2e)
(CLK to CLK# spacing)
Pair-to-Pair Spacing (e2e)
Clearance from other signals groups
Board Routing Guidelines
Total Trace Length (TTL) = (L
L + L
BREAK ROUTE
L
PKG
L
BREAK
®
Intel EP80579 Integrated Processor Product Line
Platform Design Guide
125
®
Intel EP80579 Integrated Processor Product Line—System Memory Interface (DIMM)
EP80579
EP80579
EP80579 Pin
Pad
Package
Trace
A
A#
L
PKG
Parameter
CLK/CLK#[2:0] - DIMM0; CLK/CLK#[5:3] -DIMM1
Point-to-Point
Ground Referenced
Layers 3/8 (Route Clock group on the same layer)
Single Ended Impedance: 40Ω ±10%
6.5 mils for L3/L8
6.0 mils
15.0 mils
20.0 mils
+
PKG
2.0 in - 6.0 in
)
See the Intel
for package length information
Max = 0.8 in
Differential
Board
Breakout
Routing
Routing
B
B#
L
BREAK
Routing Guidelines for 2-DIMM Solution
®
EP80579 Integrated Processor Product Line Datasheet
DIMM
C
C#
L
ROUTE
Figure
Figure 79
Figure 79,
Figure 80
Figure 80
Figure 80,
Figure 80
Figure 80
May 2010
Order Number: 320068-005US