Design Notes - Intel EP80579 Manual

EX_ALE
EX_CS[7:0]#
EX_CLK
EX_IOWAIT#
EX_RDY[3:0]#
EX_BURST
All of the signals shown in the above two tables are single ended LVTTL 3.3V logic, and
they are NOT 5V tolerant.
22.3.7

Design Notes

Care must be taken when loading the bus with too many devices. As more devices are
added, the loading capacity adds up, to the point where timing can become critical.
To account for this, timing on the expansion bus may be adjusted in the Timing and
Control Register for Chip Select. If an edge rises slowly due to low drive strength, the
processors should wait an extra cycle before the value is read. For more information,
see the documentation on Timing and Control Register for Chip Select bits [29:16] in
®
the Intel
Note: The recommendations made in this chapter is based on using a 33 MHz clock for the
LEB interface in the Development Board. If it is required to increase the clock
frequency, proper timing calculations or simulations need to be implemented to ensure
there will not be a timing issue in the design.
®
Intel EP80579 Integrated Processor Product Line
Platform Design Guide
247
®
Intel EP80579 Integrated Processor Product Line—Local Expansion Bus (LEB) Interface
Output
• Address Latch Enable
• Can be left NC when the interface is not connected
to an interfacing device or not used.
• Chip Selects 0 to 7
• External 10K ohm resistor board pull-ups are
required to ensure this signal remains deasserted.
• EX_CS[7:4]# can be configured for HPI mode of
operation. While in HPI mode, each chip select has
a corresponding EX_RDY#:
EX_CS[7]# corresponds to EX_RDY[3]# in HPI Mode
EX_CS[6]# corresponds to EX_RDY[2]# in HPI Mode
EX_CS[5]# corresponds to EX_RDY[1]# in HPI Mode
EX_CS[4]# corresponds to EX_RDY[0]# in HPI Mode
• Intel and Motorola* mode share EX_IOWAIT for all
chip selects EX_CS[7:0]#.
Input
• 33/80 MHz Expansion Bus Clock
• Must be sourced even when the interface is not
used or connected to other devices.
• Target Wait
• Must be tied high to a 10K ohm resistor when the
interface is not connected to an interfacing device
or not used.
• Bus Ready
• Must be tied high to a 10K ohm resistor when the
interface is not connected to an interfacing device
or not used.
• Burst Size
• Must be tied high to a 10K ohm resistor when the
interface is not connected to an interfacing device
or not used.
EP80579 Integrated Processor Product Line Datasheet.
May 2010
Order Number: 320068-005US