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Platform System Clock—Intel
Figure 62.
Topology for CLK14
Table 23.
CLK14 Group Routing Guidelines
Signal Group
Reference Plane
Layer Assignment
Characteristic Trace Impedance (Zo)
Nominal Trace Width
Nominal Trace Spacing
Routing Length – L1: Clock Driver to Rs
Routing Length – L2: Rs to EP80579 SIO
REFCLK total length (L1+L2)
Resistors
Skew Requirements (to other clock groups)
Figure 63.
Trace Spacing for CLK14 (REFCLK) Clocks
8.2.5
CLK48 Group
The driver in the CLK48 group is the clock synthesizer USB clock output buffer,
USB_48. The receivers are the CLK48 input buffers on the EP80579.
®
Intel
EP80579 Integrated Processor Product Line
Order Number: 320068-005US
®
EP80579 Integrated Processor Product Line
L 1
R s
C lo ck
D riv e r
Parameter
S1
L 2
Routing Guidelines
CLK14: 14 MHz Clock -- LPC_14MHz_CLK,
ICH_14MHz_CLK
Ground Referenced
Layers 8
50 Ω ±10% (single ended)
4.5 mils
Edge to Edge within CLK14 Group:10 mils
Edge to Edge not in CLK14 Group:10 mils
0.1 in. max
18 in. max
(L1+L2) to EP80579 must be within 0.500
inches of (L1+L2) to SIO
Single Load: Rs = 43 Ω ±5%
Double Load: Rs = 33 Ω ±5%
Triple Load: Rs = 12 Ω ±5%
None
W
REFCLK
S1
h
Ground Plane
E P 8 0 5 7 9
IC H _ 1 4 M H z
S IO
Figure
Figure 63
Figure 63
Figure 62
Figure 62
Figure 62
Figure 62
Figure 62
May 2010
102
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