Intel EP80579 Manual page 214

Gigabit Ethernet (GbE) Interface—Intel
Table 80. GBEn Pin Table (Sheet 4 of 4)
GBEn Signal Name
GBEn_RxDATA[3:0]
GBE_REFCLK
GBE_REFCLK_RMII
GbE RCOMP[P/N]
®
Intel EP80579 Integrated Processor Product Line
Order Number: 320068-005US
®
EP80579 Integrated Processor Product Line
Pin Pin
Type Count
RGMII Mode of Operation at 1000Base-X-speeds
• GBEn_RxDATA[3:0] signal name is GBEn_RxDATA[3:0] on the rising
edge of GBEn_RxCLK when GBEn_RxCTL is active
• GBEn_RxDATA[3:0] signal name is GBEn_RxDATA[7:4] on the falling
edge of GBEn_RxCLK when GBEn_RxCTL is active
I 4
• Pull up GBE Port 0 Receive Data signals to EP80579 2.5V Standby
Voltage (VCCSUS25) using a 1.2KΩ ± 5% resistors.
• Pull up GBE Port 1&2 Receive Data signals to GBE 2.5V using a 1.2KΩ ±
5% resistors.
• Pull-down all unused Receive Data signals to GND using 10 KΩ resistors
• The signal names GBEn_RxDATA[1:0] are mapped to
PHY_RxDATA[1:0] when the interface is configured to operate in RMII
mode of operation.
• GBEn_RxDATA[1:0] is valid on the rising edge of GBE_REFCLK on
every clock where GBEn_RxCTL is asserted, When GBEn_RxCTL is de-
asserted, GBEn_RxDATA[1:0] being equal to "00" indicates the
interface is idle.
• GBEn_RXDATA[3] signal is connected to PHY RX_ERR when operating
in RMII mode of operation.
• PHY RX_ERR (Receive Error) is driven by the PHY and asserted for one
I 4
or more GBE_REFCLK periods to indicate to the MAC that an error
(e.g., a coding error, or any error that the PHY is capable of detecting,
and that may otherwise be undetectable at the MAC sublayer) was
detected somewhere in the frame presently being transferred from the
PHY to the MAC. PHY RX_ERR shall transition synchronously with
respect to GBE_REFCLK. While GBEn_RxCTL is de-asserted, PHY
RX_ERR shall have no effect on the MAC.
• Pull up GBE Port 0 Receive Data signals to EP80579 3.3V Standby
Voltage (VCCGBEPSUS) using a 1.2KΩ ± 5% resistors.
• Pull up GBE Port 1&2 Receive Data signals to GBE 3.3V using a 1.2KΩ ±
5% resistors.
• Pull-down all unused Receive Data signals to GND using 10 KΩ resistors
• GBE_REFCLK is a continuous clock used for internal operation of the
interface when configured in RGMII mode of operation and the
interface is operating at 1000 Mb/s. This clock can be sourced from
I 1
either an external clock or from the PHY. This clock is used to produce
the GBEn_TxCLK clock.
• The GBE_REFCLK frequency is nominally 125 MHz ± 50 ppm in this
mode of operation.
• GBE_REFCLK is a continuous clock used for the internal operation of
the interface when configured in RMII mode of operation. This clock is
I 1
sourced external to both the EP80579 MAC and PHY.
• The GBE_REFCLK frequency is nominally 50 MHz ± 50 ppm in this
mode of operation.
• GBE_REFCLK_RMII is unused and connected via a 100Ω +/- 1% tolerance
I 1
resistor to ground when the interface is configured in RGMII mode of
operation.
• GBE_REFCLK_RMII is connected to the same clock source as the
GBE_REFCLK when the interface is configured in RMII mode of
I 1
operation.
• The GBE_REFCLK/GBE_REFCLK_RMII frequency is nominally 50 MHz ±
50 ppm in this mode of operation.
• Signal used to control Gigabit Ethernet (RMII/RGMII mode) drive
strength characteristics. Drive strength is varied on GbE Ethernet
signals depending upon temperature.
I/O 2
• GbE RCOMPP requires 50Ω +/- 1% tolerance resistor to ground.
• GbE RCOMPN requires 50Ω +/- 1% tolerance resistor to EP80579 GbE 2.5V
Standby Voltage (VCCSUS25).
Description
RMII Mode of Operation:
RGMII Mode of Operation:
RMII Mode of Operation:
RGMII Mode of Operation:
RMII Mode of Operation:
May 2010
214