Intel EP80579 Manual page 22

Table 2. Acronyms and Terminology (Sheet 2 of 3)
Acronym
EDMA
EMI
EMTS
ESD
FRU
FS
FSB
FWH
HBA
HCD
HECBASE
HSI
IA
IA-32 core
2
I C
2
I S
ICE
ICH
IICH
IMCH
I/O
IP
ITP-XDP
JEDEC
LEB
LPC
LS
LSb
LSB
MCH
MMIO
MSb
MSB
MSI
MTBF
NCM
NSI
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Intel EP80579 Integrated Processor Product Line
Platform Design Guide
22
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Intel EP80579 Integrated Processor Product Line—Introduction
Definition
Enhanced DMA
Electro Magnetic Interference
Electrical Mechanical Thermal Specification, used for processor specifications.
Electrostatic Discharge
Field Replaceable Unit
Full-speed, refers to USB.
Front Side Bus (a common external interface for Intel
Firmware Hub, a non-volatile memory device used to store the system BIOS.
Host Bus Adapter, necessary when connecting a peripheral to a computer that doesn't
have native support for that peripheral's interface.
Host Controller Device, a USB interface for programmers
PCI Express Enhanced Configuration Base Register
High Speed Interface, refers to USB.
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Intel Architecture instruction set commonly known as "x86"
High performance processor based on the 32-bit embedded Intel
processor
Inter-IC Control
Integrated Interchip-Sound
In-Circuit-Emulator- JTAG based Emulator to debug software on an embedded system
I/O Controller Hub
Integrated I/O Controller Hub
Integrated Memory Controller Hub
1. Input/Output
2. When used as a qualifier to a transaction type, specifies that transaction targets Intel
architecture-specific I/O space (e.g., I/O read).
Internet Protocol
In Target Probe - Expanded Debug Port
Joint Electron Device Engineering Council, solid state technology forum
Local Expansion Bus - EP80579 internal bus to external expansion target devices such as
external memory or other physical layer devices.
Low Pin Count
Low-speed, refers to USB.
Least Significant Bit
Least Significant Byte
Memory Controller Hub
Memory Mapped I/O
Most Significant Bit
Most Significant Byte
Message Signaled Interrupt that encodes interrupts as an in-band 32-bit write transaction.
Mean Time Between Failures
Non Coherent Memory
North South Interface, the designation for the proprietary, internal high-speed serial
interconnect between the IMCH and the IICH.
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architecture (IA) processors)
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Architecture (IA-32)
May 2010
Order Number: 320068-005US
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