Figure 31. Intel 855Pm Mch Hvref[4:0] Reference Voltage Generation Circuit - Intel 855PM Design Manual

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Figure 31. Intel 855PM MCH HVREF[4:0] Reference Voltage Generation Circuit

A recommended layout for the MCH_GTLREF generation circuit is shown in Figure 32. The
MCH_GTLREF generation circuit components are located on the secondary side to minimize
motherboard space usage and optimize robustness of the connection. Each of the AB16, AB12, and P8
HVREF pins has a decoupling capacitor (C1, C2, and C3) next to them. GND side of the C1, C2, and
C3 capacitors is connected to the GND flood on the secondary side and stitched with vias to internal
GND planes. R1 is placed next to pin AB16 and R2 is placed next to pin P8. Layer 3 of the motherboard
shorts the two clusters of HVREF pins P8, M7, AB16, AB12, and AA9. The two clusters are further
shorted on the primary side layer.
®
Intel 855PM Chipset Platform Design Guide
+VCCP
R1
Ω
1%
MCH_GTLREF
R2
C1 C2
Ω
200 pF 200 pF
1%
AB16
HVREF
AB12
HVREF
C3
AA9
HVREF
1 uF
P8
HVREF
M7
HVREF
FSB Design Guidelines
Intel
855PM
MCH
67