Address/Command Daisy Chain With Parallel Termination Topology Diagram; Ddr2 Address/Command Signal Group Routing Guidelines - Intel EP80579 Manual

System Memory Interface (DIMM)—Intel
Figure 82.

Address/Command Daisy Chain With Parallel Termination Topology Diagram

EP80579
EP80579
Pad
Package
L
PKG
Table 46. DDR2 Address/Command Signal Group Routing Guidelines (Sheet 1 of 2)
Signal Group
Topology
Reference Plane
Layer Assignment
Characteristic Trace Impedance (Zo)
Nominal Trace Width
Nominal Trace Spacing (e2e)
Clearance from other signals
Board Routing Guidelines
Total Trace Length (TTL) = (L
L + L
BREAK
L
PKG
L
BREAK
L
ROUTE
L
D2D
L
TERM
®
Intel EP80579 Integrated Processor Product Line
Order Number: 320068-005US
®
EP80579 Integrated Processor Product Line
EP80579
Pin
Breakout
Board
Trace
Routing
Routing
C
A
B
L
BREAK
Parameter
DDR_MA[14:0], DDR_BA[2:0], DDR_RAS#,
DDR_CAS#, DDR_WE#
Daisy Chain
Ground Referenced
Layers 3/8
40 Ω ±10%
6.5 mils
15 mils
20 mils (min)
+
PKG
2.0 in - 6.0 in
+ L + L )
ROUTE D2D TERM
See the Intel
for package length information.
Max = 0.8 in
Max = 4.0 in
Max = 0.8 in
Max = 500 mils
DIMM 1
Dimm2Dimm
Routing
D
Ccomp
L
L
ROUTE
Routing Guidelines for 2-DIMM Solution with
ODT
®
EP80579 Integrated Processor Product Line Datasheet
• Trace length skews for the control signal for DIMM-to-DIMM
routing should not exceed 10 mils
• Trace length skews for the ADD/CMD signals to the termination
resistors (L ) should not exceed 200 mils.
TERM
DIMM 0
VTT_DDR
E
L
D2D
TERM
Figure
Figure 76
Figure 82
Figure 82
Figure 82
May 2010
130