Intel EP80579 Manual page 23

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Introduction—Intel EP80579 Integrated Processor Product Line
Table 2. Acronyms and Terminology (Sheet 3 of 3)
Acronym
OS
P2P
PCI
PCM
PEC
PIRQx
PLL
POC
RDMA
RFL
RMW
RTC
RTCRESET#
SATA
SATA*
SEC
SEC/DED
SM
SMBus
SMM
SPD
STR
TAP
TCP
TDM
TDR
TFL
USB
VCC
VCXO
VDD
VREF
VSS
VTT
WDT
XDP
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Intel EP80579 Integrated Processor Product Line
Order Number: 320068-005US
Definition
Operating System
Peer-to-Peer
Peripheral Component Interconnect Local Bus, a 32- or 64-bit bus with multiplexed
address and data lines that is primarily intended for use as an interconnect mechanism
within a system between processor/memory and peripheral components or add-in cards.
Pulse Code Modulation
Packet Error Checking, this is an SMBus 2.0 feature
Legacy PCI interrupt architecture that encodes interrupts on one of eight side-band signals
(PIRQ[H:A]).
Phase-Locked Loop
Power On Configuration
Remote Direct Memory Access
Receive FIFO Level
Read-Modify-Write operation
Real-Time Clock
Signal that resets the RTC well (but does not clear the RTC RAM memory contents).
Serial Advanced Technology Attachment
Serial ATA, an industry specification of the interface for storage controllers and devices.
Single-bit Error Correct
Single Error Correct/Double Error Detect, a specific data protection algorithm that
distributes data and ECC across 144 bits. Enables correction of single bit errors. Allows
detection of double bit errors.
M-Unit attached to the System Memory (Convention taken from IA CHAP event definition)
System Management Bus
System Management Mode
Serial Presence Detect
Suspend To RAM
Test Access Port used for testability and debug of the component
Transmission Control Protocol
Time Division Multiplexed
Time Domain Reflectometry
Transit FIFO Level
Universal Serial Bus
Used to signal circuit logic voltage
Voltage Controlled Crystal Oscillator
Used to signify DIMM logic supply voltage
Voltage Reference
Used to signify ground connection
Used to signify signal termination voltage
Watch Dog Timer
eXtended Debug Port
May 2010
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