Leb Memory Size (Leb_Size) Strapping; Leb Interface Topologies; Leb Interface Topology At 33 Mhz - Intel EP80579 Manual

Local Expansion Bus (LEB) Interface—Intel
EX_CS4#
EX_CS5#
EX_CS6#
22.2

LEB Memory Size (LEB_SIZE) Strapping

As stated above, the LEB controller allocates up to 256 MB of memory space to support
up to 8 devices on the LEB Bus. At power-up or whenever RESET_IN# is asserted,
EX_ADDR[23:21] bits are captured and stored by the LEB controller to detemine the
LEB memory size (LEB_SIZE) and the number of devices supported on the bus. The
EX_ADDR[23:21] should be externally strapped with 1K ohm pull-ups and pull-downs
to determine the LEB_SIZE as shown in
Table 87.

LEB Memory Size (LEB_SIZE) Strapping

LEB_SIZE
[23 : 21]
000
001
010
011
1xx
Note: Only 8 chip selects are supported; the other 8 are alias of the first 8 chip selects. Refer to the Utilizing
the Local Expansion Bus on the Intel® EP80579 Integrated Processor Product Line Application Note,
Document Number 321096 for details.
22.3

LEB Interface Topologies

There are three groups of signals that require careful routing when designing with the
LEB interface. These groups are split into Chip Select, Address, and Data/Control
signals. The following sections recommend guidelines to help design a working system
that will minimize signal integrity issues. The recommendations are based on the
Development Board routing with the LEB clock rate at 33 MHz.
22.3.1

LEB Interface Topology at 33 MHz

The Development Board has been designed to interface with up to 7 devices, which are
split in two bridges. The primary bridge interconnects with the first four peripherals and
a buffer, while the secondary bridge interconnects with three mezzanine connectors.
The connectors are to be used to interface with existing line cards and future develop
cards. With careful routing and following the guidelines in this chapter, this topology
can run at a maximum speed of 33 MHz.
®
Intel EP80579 Integrated Processor Product Line
Order Number: 320068-005US
®
EP80579 Integrated Processor Product Line
Chip Select Signal
MMBAR
Size
0 MB
32 MB
64 MB
128 MB
256 MB
Peripheral
Mezzanine Connector 1
Mezzanine Connector 2
Mezzanine Connector 3
Table 87.
# of CS
"+ 16 MB" mode
None
2
4
8
16 (See Note)
# of CS
"+ 32 MB" mode
None
1
2
4
8
May 2010
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