Intel EP80579 Manual page 274

Table 97. Layout Checklist (Sheet 6 of 13)
Signal Name
GP3_PIRQF#
GP4_PIRQG#
GP5_PIRQH#
GPIO[10:6]
GP11_SMBALERT#
GPIO[21:12]
GPIO[25:23]
GP26_SATA0GP
GPIO[28:27]
GP29_SATA1GP
GPIO[31:30]
GPIO[34:33]
GPIO[40]
GP41_LDRQ[1]#
GPIO[48]
IICH Interrupts
SERIRQ
LAD[3:0], LFRAME#
LDRQ[0]#
GP41_LDRQ[1]#
PCICLK
SPI_MOSI
SPI_MISO
®
Intel EP80579 Integrated Processor Product Line
Platform Design Guide
274
®
Intel EP80579 Integrated Processor Product Line—Layout Checklist
Trace Geometry and
Impedance
Zo = 50 Ω +/- 10%
Ω
Zo = 50 +/- 10%
Ω
Zo = 50 +/- 10%
Ω
Zo = 50 +/- 10%
Ω
Zo = 50 +/- 10%
Ω
Zo = 50 +/- 10%
Ω
Zo = 50 +/- 10%
Ω
Zo = 50 +/- 10%
Ω
Zo = 50 +/- 10%
Ω
Zo = 50 +/- 10%
Ω
Zo = 50 +/- 10%
Ω
Zo = 50 +/- 10%
Ω
Zo = 50 +/- 10%
Ω
Zo = 50 +/- 10%
Ω
Zo = 50 +/- 10%
Ω
Zo = 50 +/- 10%
Low Pin Count (LPC) Interface
Ω
Zo = 50 +/- 10%
Ω
Zo = 50 +/- 10%
Ω
Zo = 55 +/- 10%
Trace Width:
Microstrip: 4.5 mils
Stripline: 3.75 mils (L3/L8)
Airgap Spacing:
Spacing to other signals 20 mils
Serial Peripheral Interface (SPI) - System BIOS Topology
Ω
Zo = 50 +/- 10%
Trace Width:
Microstrip: 4.5 mils
Stripline: 3.75 mils (L3/L8)
Airgap Spacing:
Spacing to other signals 7 mils
Ω
Zo = 50 +/- 10%
Trace Width:
Microstrip: 4.5 mils
Stripline: 3.75 mils (L3/L8)
Airgap Spacing:
Spacing to other signals 7 mils
Length Requirements
Routing Length LT:
LT = 2 in - 20 in.
See
Routing Length LT: Guidelines".
Max = 16 in. Place pull resistor close to the
SPI Flash device.
See
Routing Length LT: Guidelines".
Max = 16 in. Place pull resistor close to the
SPI Flash device.
Comments
Section 16.2.1, "SPI Routing
Section 16.2.1, "SPI Routing
May 2010
Order Number: 320068-005US