Write Operation Odt Table - Intel EP80579 Manual

System Memory Interface (DIMM)—Intel
Table 42. DDR2 Control Signal Group Routing Guidelines (Sheet 2 of 2)
Clearance from other signals
Board Routing Guidelines
Total Trace Length (TTL) = (L
L + L
BREAK
L
PKG
L
BREAK
L
ROUTE
L
D2D
L
TERM
On-Board Termination
Parallel Termination Resistor (Rtt)
Length/Skew Matching Rules
Length Tuning Requirements
9.7.1.3.1 ODT Settings
Table 43
and read operations to/from single-rank (SR) and dual-rank (DR) DIMM modules.
Table 43.

Write Operation ODT Table

DIMM
Module
DIMM 0 DIMM 1
SR
DR
DR
SR
SR
®
Intel EP80579 Integrated Processor Product Line
Order Number: 320068-005US
®
EP80579 Integrated Processor Product Line
Parameter
20 mils (min)
+
PKG
(TTL of CMD/ADD) + 2.5 in ±5% (See
+ L + L )
ROUTE D2D TERM
See the Intel
for package length information.
Max = 0.8 in
Calculate from Total Trace Length
Max = 0.8 in
Max = 500 mils
60 Ω ±1%
and Table 44 provides the DDR2 Controller and DIMM ODT settings for write
Write Controller
Target Configuration
Empty Rank0
Empty Rank0
Empty Rank1
SR Rank0
SR Rank1
Routing Guidelines for 2-DIMM Solution with
ODT
®
EP80579 Integrated Processor Product Line Datasheet
• Trace length skews for the control signal for DIMM-to-DIMM
routing should not exceed 10 mils
• Trace length skews for the control signals to the termination
resistors (L ) should not exceed 200 mils.
TERM
• The control signals need to match in length within
± 20 mils of each other.
DIMM 0
Configuration
Rank0
ODT Off 75 Ω
ODT Off ODT Off
ODT Off 75 Ω
ODT Off ODT Off
ODT Off 75 Ω
Figure
Table 46)
Figure 81
DIMM 1
Configuration
Rank1 Rank0 Rank1
n/a n/a
75 Ω n/a
ODT Off n/a
n/a 75 Ω
n/a ODT Off
May 2010
n/a
n/a
n/a
n/a
n/a
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