Intel EP80579 Manual page 4

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5.8.4
Signals Crossing Plane Splits................................................................................ 63
6.0
System Power Delivery Guide....................................................................................................... 64
6.1
Terminology and Definitions ............................................................................................... 64
6.2
Power Supply...................................................................................................................... 65
6.3
Power Planes...................................................................................................................... 66
6.4
Power Requirements .......................................................................................................... 67
6.5
Power Delivery Guidelines.................................................................................................. 69
6.5.1
IA-32 core Power (VCC_CPU) .............................................................................. 69
6.5.2
Core Logic Voltage (V1P2) .................................................................................... 70
6.5.3
DDR2 Voltage (V1P8_DDR).................................................................................. 70
6.5.4
DDR2 Termination Voltage (DDR2_VTT).............................................................. 70
6.5.5
1.8V Voltage (V1P8) .............................................................................................. 70
6.5.6
GbE 2.5V (V2P5) ................................................................................................... 70
6.5.7
3.3V (VCC3) .......................................................................................................... 71
6.5.8
5V Voltage (VCC50) .............................................................................................. 71
6.5.9
VCCRTC Reference .............................................................................................. 71
6.5.10 Standby Voltages................................................................................................... 71
6.5.11 Auxiliary Voltages .................................................................................................. 72
6.6
Component Power Distribution Guidelines ......................................................................... 72
6.6.1
IA-32 core Power Distribution Guidelines .............................................................. 72
6.6.2
6.6.3
Voltage Regulator Design Recommendations....................................................... 73
6.6.4
Power Plane Filter Requirements .......................................................................... 77
6.6.5
Analog and Bandgap Filter Layout Guidelines ...................................................... 79
6.6.6
Analog and Bandgap Filter Frequency Response ................................................. 79
6.6.7
Thermal Power Dissipation.................................................................................... 80
6.7
Decoupling Recommendations........................................................................................... 81
6.7.1
VCCVC (IA-32 core Power) Decoupling ................................................................ 81
6.7.2
VCC (1.2V Core Logic) Decoupling ....................................................................... 81
6.7.3
VCCA[2:1] (1.2V, IA-32 core PLL Power) Decoupling........................................... 81
6.7.4
VCCAPE (1.2V, PCI Express Power) Decoupling ................................................. 82
6.7.5
VCC18 (1.8V - DDR2) Decoupling ........................................................................ 82
6.7.6
VTTDDR (0.9V - DDR2_VTT) Decoupling............................................................. 82
6.7.7
V1P8_DDR (DIMM) Decoupling (CRB Power Reference) .................................... 82
6.7.8
VCC33 (3.3V) Decoupling ..................................................................................... 82
6.7.9
VCC25 (2.5V GbE Voltage) Decoupling ................................................................ 82
6.7.10 VCC50 (5.0V Reference) Decoupling.................................................................... 83
6.7.11 VCCPRTC (Battery Power) Decoupling ................................................................ 83
6.7.12 VCC50_SUS (5.0V Standby logic) Decoupling ..................................................... 83
6.7.13 VCCPSUS (3.3V Standby logic) Decoupling ......................................................... 83
6.7.14 VCCSUS25 (2.5V Standby logic) Decoupling ....................................................... 83
6.7.15 VCCSUS1 (1.2V Standby logic) Decoupling ......................................................... 83
7.0
Power Management and Reset Interface ..................................................................................... 84
7.1
Reset and Powergood Distribution ..................................................................................... 84
7.1.1
Types of Reset....................................................................................................... 84
7.1.2
Powergood Implementation ................................................................................... 84
7.1.3
Hard Reset Implementation ................................................................................... 84
7.1.4
Software Controlled Reset..................................................................................... 85
®
Intel
EP80579 Integrated Processor Product Line
4
®
Intel
EP80579 Integrated Processor Product Line-Contents
May 2010
Order Number: 320068-005US

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