Chip Select Point-To-Point Topology Diagram; Chip Select Point-To-Point Topology Routing Guidelines - Intel EP80579 Manual

Local Expansion Bus (LEB) Interface—Intel
Figure 147
routing chip select signals.
Figure 147. Chip Select Point-to-Point Topology Diagram
Chip Select Point-to-Point Topology
EP80579
Break out
Via
CS
LCS_Brk_out
L
CS_Total
NOTE: Breakout\ Breakin descriptions are as follows:
1. Routing where trace is 4 mil wide and 4mil spacing is implemented to escape\ enter BGA
2. The Breakout \ Breakin Length is defined from the pin of the BGA, to where 4 mil spacing
increases to the required spacing per SI recommendations.
a). CS = 10 mil edge-to-edge (e2e) for Stripline
b). CS = 12 mil edge-to-edge (e2e) for Microstrip
Table 89. Chip Select Point-to-Point Topology Routing Guidelines (Sheet 1 of 2)
Routing Layer
Reference Plane
Board Trace Impedance
Trace Width
Chip Select to Other Signals Spacing
®
Intel EP80579 Integrated Processor Product Line
Order Number: 320068-005US
®
EP80579 Integrated Processor Product Line
and Table 89 indicate min and max trace lengths that can be used when
(EP80579
22 ohm 1%
LCS_Brd_route
L
= CS_Brk_out +
Parameter
Peripheral)
VCC3
Rpull_up
10K ohm
Board Break in
LCS_Brk_in
L
CS_Brd_route +
Routing Constraints
Stripline
Ground Referenced
50 Ω
4.5mils (L3/L8)
10 mils (min)
Peripheral
Via
CS
L
CS_Brk_in
Microstrip
50 Ω
5.5mils (L1/L10)
12 mils (min)
May 2010
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