Intel EP80579 Manual page 15

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Contents-Intel EP80579 Integrated Processor Product Line
73 SPI Single Flash Device Routing Summary .........................................................................200
74 Boot-up Strapping Options (Flash) .......................................................................................201
75 GPIO Pin Definitions ............................................................................................................202
76 Development Board GPIO Usage ........................................................................................203
77 Interrupt Configurations - APIC Mode ..................................................................................204
78 SIU Interface Signals............................................................................................................206
79 Frequencies of All Input Clocks............................................................................................210
80 GBEn Pin Table....................................................................................................................211
82 GbE MAC Serial EEPROM Interface Signals.......................................................................215
81 GbE MAC Management Data Interface Signals...................................................................215
83 GbE RGMII Transmit Path Clock Routing Guidelines ..........................................................220
84 GbE RGMII Transmit Path Data\Control Routing Guidelines ...............................................222
85 GbE RGMII Receive Path Clock Routing Guidelines ...........................................................224
86 GbE RGMII Receive Path Data\Control Routing Guidelines ................................................226
87 LEB Memory Size (LEB_SIZE) Strapping ............................................................................238
88 Multi-drop Topology Trace Lengths for the Development Board..........................................239
89 Chip Select Point-to-Point Topology Routing Guidelines .....................................................240
90 Address, Data and Control Star Topology Routing Guidelines ............................................244
91 Address, Data and Control Star Topology Routing Guidelines ............................................245
92 Sideband Signals ................................................................................................................254
93 Routing Recommendations for Sideband Signals................................................................257
94 Terms and Definitions ..........................................................................................................258
95 XDP To EP80579 Signal Connections .................................................................................265
96 Signal Type Definitions.........................................................................................................268
97 Layout Checklist ...................................................................................................................269
98 CK410 Schematic Checklist .................................................................................................282
99 Signal Type Definitions.........................................................................................................283
100 Schematic Checklist .............................................................................................................284
101 Decoupling Recommendations ............................................................................................310
102 CK410 Schematic Checklist .................................................................................................312
A-1 DDR Terminology.................................................................................................................317
A-2 Supported SODIMM Memory Capacity for 64-bit Mode.......................................................317
A-3 DDR2 Unbuffered SODIMM and Unbuffered DIMM Pin Comparison Table ........................318
A-4 DDR2 Signal Groups............................................................................................................319
A-5 Length Matching Formulas between EP80579 and DDR2 SODIMM ...................................320
A-6 Data and Strobe Signal Group Routing Guidelines..............................................................322
A-7 Clock Signal Group Routing Guidelines ...............................................................................324
A-8 Write Operation ODT Table..................................................................................................325
A-9 Read Operation ODT Table .................................................................................................326
A-10 DDR2 Control Signal Group Routing Guidelines..................................................................327
A-11 Address and Command Signals...........................................................................................327
A-12 DDR2 Address/Command Signal Group Routing Guidelines ..............................................328
A-13 DDR V Generation Requirements ..................................................................................331
REF
A-14 Write Levelization for Single Rank Configuration .................................................................332
A-15 Write Levelization for Dual Rank Configuration....................................................................332
B-16 DDR Terminology.................................................................................................................333
B-17 Supported DDR2 Device Densities and Widths ...................................................................334
B-18 Supported DRAM Capacity for 64-bit Mode .........................................................................334
B-19 Supported DRAM Capacity for 32-bit Mode .........................................................................335
B-20 256Mb Addressing ...............................................................................................................335
May 2010
Order Number: 320068-005US
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Intel EP80579 Integrated Processor Product Line
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