Data And Strobe Signal Group Routing Guidelines - Intel EP80579 Manual

System Memory Interface (DIMM)—Intel
Table 39. Data and Strobe Signal Group Routing Guidelines (Sheet 2 of 2)
Board Routing Guidelines
Total Trace Length (TTL) = (L
L + L
BREAK
L
PKG
L
BREAK
L
ROUTE
L
D2D
Length/Skew Matching Rules
Length Tuning Requirements
Routing Rules
Layer Routing Requirements
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Order Number: 320068-005US
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EP80579 Integrated Processor Product Line
Parameter
+
PKG
2.0 in - 6.0 in
+ L )
ROUTE D2D
See the Intel
package length information.
B = 0.8 in (max)
C = 2.0 in - 4.0 in
D = 0.8 in (max) (including both DIMMs' break-in fields)
• Only length matching
• DQ/DM should match
• Length match all DIMM-to-DIMM (D2D) signals (DQ/DM/DQS/DQS#)
Signals within a data byte lane must be routed on the
same layer.
Routing Guidelines
Data Byte Lane
Data & Data Mask
Max TTL (DQS/DQS#) =
Min TTL (DQ/DM) +
400 mils
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EP80579 Integrated Processor Product Line Datasheet for
Calculate while taking into
account Strobe Max Trace
Length (Max TTL)
• The trace length
is required within each
Byte lane. No signal
length matching is
required outside the
DQS[x] =
Byte lane. For
DQS[x]#±10 mils, x = 0..
example, any signal
8
within Data Byte Lane
0 (DQ [0...7]) need not
be length matched to • Length match the data
DQS1
each other to 20 mils
or less within the same
byte lane. (See
Figure 78) Max(DQS/DQS#) =
Min(DQ/DM[x]) +
400 mils, x = 0.. 8
to 10 mils or less within the same byte lane
Figure
Strobe
Figure 77
difference between
DQS and DQS# should
not be more than 10
mils. - that is,
strobes (DQS/DQS#)
to the associated data
mask and data (DQ/
DM) signals for each
Data Byte Lane:
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