Board Stack-Up Consideration - Intel EP80579 Manual

Mode conversions are due to imperfections and other trace mismatches on the
interconnect which transform differential mode voltage to common mode voltage and
vice versa. For example, length mismatch within pairs or an asymmetric via layout
could cause mode conversion.
Differential signaling is that in which information is encoded in the difference between
the voltage on two nets. The differential receiver is designed to be very sensitive to this
difference, while being insensitive to portions of the signal that are similar (the
common-mode signal). It is important to equalize the total length of the traces in the
pair throughout the trace; each segment of trace length must be equal along the entire
length of the pair. The differential trace impedance target of 90 Ω ±10%, unless
otherwise specified. Tight coupling within the differential pair and increased spacing to
other differential pairs helps to minimize EMI and crosstalk. It is preferable to route Tx
and Rx differential pairs alternately on the same layer (i.e., a Tx pair next to an Rx pair
rather than another Tx pair) to help minimize FEXT at the receiver on microstrip layers.
For coupled differential pairs, every attempt should be made to match the number of
left and right bends as closely as possible to minimize skew due to length differences
between each signal of the differential pair.
Alternate left and right turns to minimize skew due to length differences between each
signal of the differential pair. Matching the number of right and left turns and
alternating such bends helps to minimize the amount of skew between rising or falling
edges of a propagating differential signal pair at any point along the length of the pair.
For example, a series of left turns adds length to the outside trace that increases the
delay of that trace. Although this length could potentially be made up at the end of the
trace route, thereby ensuring that the signal pair is in sync at both the beginning and
the end of the trace route, the signal pair is actually out of sync in the area around the
series of left turns.
Trace segment length matching within pairs is required to ensure trace lengths are
equal on a segment-by-segment basis. Overall length must match to +/- 5 mils.
Examples of segments could include breakout areas, routes between two vias, routes
between an AC coupling capacitor and a connector pin, etc. The points of discontinuity
would be the via, the capacitor pad, or the connector pin. In addition, length
mismatches must be corrected closely following the mismatch site to minimize common
mode conversion effects.
When routing traces, bends must be kept to a minimum. If bends cannot be avoided,
they must be at a 45° angle or smaller, do not use 90-degree bends or turns.
10.1.1

Board Stack-Up Consideration

Generally the stack-up depends on the following:
• Signal referencing
• Power-ground plane decoupling requirements
• Routing channel requirements
Due to frequency-dependent loss effects at PCI Express edge rates, the guidelines in
this section apply only to the reference stackup. Even if trace widths are adjusted to
meet the specified impedance targets, the attenuation of high frequency components
of the signal on those traces is a function of the trace width and thickness as well as
dielectric characteristics. A design that deviates from the specified stackup will require
simulation and validation of the proposed PCI Express implementation. Simulation is
highly recommended for all PCI Express implementations.
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Intel EP80579 Integrated Processor Product Line
Platform Design Guide
137
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Intel EP80579 Integrated Processor Product Line—PCI Express* Interface
May 2010
Order Number: 320068-005US