Additional Considerations For Pci Express; Pci Express I/O Devices; Emi; Pci Express Down Device With Lai Connector Routing (Ep80579 Receive) - Intel EP80579 Manual

PCI Express* Interface—Intel
Table 56.

PCI Express Down Device with LAI Connector Routing (EP80579 Receive)

Trace Length L2, L2' – AC CAP to logic
analyzer breakout region.
Trace Length L3, L3', L4, L4' – Logic
analyzer breakout region.
Trace Length L5, L5' – Logic analyzer
breakout region to PCI Express device
breakout region.
Trace Length L6, L6' – PCI Express
breakout region.
Trace Length LT– EP80579 pin to PCI
Express Device
Length Tuning Requirements
Figure 97.

PCI Express Down Device With LAI Connector Routing (EP80579 Receive)

EP80579
10.2

Additional Considerations for PCI Express

10.2.1

PCI Express I/O Devices

Baseboard down PCI Express I/O devices typically require special layout techniques on
other data interfaces as well. Keep the considerations in this section in mind and
reference the appropriate design guides while performing the PCI Express layout.
10.2.2

EMI

As data is transmitted at higher frequencies, the spectrum of high-speed signals has
significant energy as the speed reaches several GHz. Minimizing and containing EMI is
challenging for wide band signals. There are two general principles for EMI reduction in
a system:
• Suppression of noise generation
®
Intel EP80579 Integrated Processor Product Line
Order Number: 320068-005US
®
EP80579 Integrated Processor Product Line
Parameter
LT = L1 + L2 + L3 + L4 + L5 + L6
L1
AC CAP
L1'
AC CAP
Routing Guidelines
Min = 0.5 in.
Max = 5.5 in.
0.5 in. (stripline)
Min = 2.5 in.
Max = 6.5 in.
Min = 0.75 in.
Max = 2.0 in.
LT = L1+L2+L3+L4+L5+L6 (stripline)
LT = L1+L2+L5+L6 (microstrip)
Routing must remain on the same layer.
Maximum number of vias is 6 (stripline) and 4
(microstrip).
LT-LT' = ±5 mils
LAI
Connector
L2 L3 L4
LAI
Connector
L2' L3' L4' L5' L6'
Figure
Figure 97
Figure 97
Figure 97
Figure 97
Figure 97
Figure 97
PCI
L5 L6
Express*
Device
May 2010
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