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Platform System Clock—Intel
8.2.2
CLK100 (SRC Clock) Group
The differential 100 MHz clock synthesizer (SRC) is the source to the PCI Express, SATA
and an input to the DB800 differential buffer. The DB800 buffer provides outputs to the
PCI Express I/O components.
8.2.2.1
SRC/SRC# General Routing Guidelines
• Do not split up the two halves of a 100 MHz differential clock pair between layers
and route to all agents on the same physical routing layer referenced to ground.
• Individual clock pairs must be matched to within ±25 mils, though no length
matching is required between different source pairs.
• Do not place vias between adjacent complementary clock traces and avoid layer
transitions. Vias placed in one half of a differential pair must be matched by vias in
the other half. Differential vias can be placed within length L1, between clock driver
and Rs, if needed to shorten length L1.
8.2.2.2
SRC Clock Topology
The CK410 clock synthesizer provides six sets of 100 MHz differential Serial Reference
Clock (SRC) outputs. The 100 MHz differential clocks are driven to the SATA and PCI
Express ports as well as PCI Express slots or components. See
The clock driver differential bus output structure is a "current mode current steering"
output, which develops a clock signal by alternately steering a programmable constant
current to the external termination resistors, designated as Rt. The resulting amplitude
is determined by multiplying IOUT by the value of Rt. The current IOUT is
programmable by a resistor and an internal multiplication factor, so the amplitude of
the clock signal can be adjusted for different values of resistance to match impedances
or to accommodate future load requirements.
The recommended termination for the differential bus clock is a "shunt source
termination." See
resistors perform a dual function, converting the current output of the clock driver to a
voltage and matching the driver output impedance to the transmission line. The series
resistors, designated as Rs, provide isolation from the clock driver's output parasitics,
which would otherwise appear in parallel with Rt.
The value of Rt must be selected to match the characteristic impedance of the
baseboard.
®
Intel
EP80579 Integrated Processor Product Line
Order Number: 320068-005US
®
EP80579 Integrated Processor Product Line
Figure 55
for an illustration of this terminology scheme. Parallel Rt
Figure
52.
May 2010
96
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