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Schematics Checklist—Intel
Table 100.
Schematic Checklist (Sheet 5 of 26)
Checklist Items
PEA_CLKp,
PEA_CLKn
PEA_ICOMPI,
PEA_ICOMPO,
PEA_RCOMPO
Real Time Clock (RTC)
RTCX1,
RTCX2
RTEST#
GPIO[1:0]
GP2_PIRQE#
GP3_PIRQF#
GP4_PIRQG#
GP5_PIRQH#
GPIO[7:6]
®
Intel
EP80579 Integrated Processor Product Line
Order Number: 320068-005US
®
EP80579 Integrated Processor Product Line
I/O Type
Recommendations
(Default)
• Connect to one of 100 MHz
differential clock outputs from
CK410 Clock device through a
I
33 Ω ±5% series resistor.
• Terminate to GND through a
49.9Ω ±1% resistor
• Tie these signals together and
connect to EP80579 1.2V (VCC)
I
supply through a 24.9 Ω ±1%
resistor.
Integrated I/O Controller Hub (IICH) Interface
RTC Crystal I/O
• Connect a 32.768 kHz Crystal
Oscillator across these pins
I/O
with a 10 MΩ resistor.
• Decouple both RTCX1 and
RTCX2 with 15 pF ±5%, 50V
capacitors to GND.
RTC Test Enable
• Connect pin to a 20KΩ ± 5%
I
resistor to VCCRTC.
• Connect to a 1.0µF ± 5%
capacitor to GND.
General Purpose I/O (GPIO) and Interrupts Interface
I
• Input Only (GPI)
• Input Only if used as GPI.
I
• Can be used as PIRQE#.
• Input Only if used as GPI.
I
• Can be used as PIRQF#.
• Input Only if used as GPI.
I
• Can be used as PIRQG#.
• Input Only if used as GPI.
I
• Can be used as PIRQH#.
I
• Input Only (GPI)
Comments
Note:
• Connect PEA_CLK(p/n) to a
100 MHz differential clock source
even if the PCI-E port is not used or
not connected to an interfacing
device.
• See
Section 2.3
Note:
• The capacitor and resistor values in
this document is based on the
crystal selected for the
Development Board.
• The exact capacitor and resistor
values for any design must be
based on the recommendations
provided by the crystal maker for
the crystal selected for the design
• See
Figure 130
for further
guidelines
See
Section
15.1.5.
• Must be pulled high through a 10
KΩ resistor if not used
• Resides in Core Power Well
• Must be pulled high through a 10
KΩ resistor if not used or used in
PIRQ mode.
• Resides in Core Power Well
• Must be pulled high through a 10
KΩ resistor if not used or used in
PIRQ mode.
• Resides in Core Power Well
• Must be pulled high through a 10
KΩ resistor if not used or used in
PIRQ mode
• Resides in Core Power Well
• Must be pulled high through a 10
KΩ resistor if not used or used in
PIRQ mode
• Resides in Core Power Well
• Must be pulled high through a 10
KΩ resistor if not used
• Resides in Core Power Well
May 2010
288
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