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25.0
Sideband Signals
Table 92
describes the EP80579
Table 92.
Sideband Signals (Sheet 1 of 4)
Signal Name
CPUSLP_OUT#
INIT33V_OUT#
®
Intel
EP80579 Integrated Processor Product Line
Platform Design Guide
254
®
Intel
EP80579 Integrated Processor Product Line—Sideband Signals
IA-32 core legacy and miscellaneous signals.
'S
Group
CPU Sleep:
• This EP80579 output signal is made visible to the
CPU Sideband Output
• This signal can be monitored via a LED.
• Pull up signal to Platform 3.3V (VCC3) power supply
Note:
• This signal can be left as a no connect (NC) if not
CPU Initialization:
• This 3.3V EP80579 output signal is made visible to
FWH Reset
• Connect to FWH INT# pin.
• Pull up signal to Platform 3.3V (VCC3) power supply
Note:
• This signal can be left as a no connect (NC) if not
Description
platform for debug purposes only. This internal
EP80579 signal places the processor into a state
that saves substantial power compared to the Stop-
Grant state. When EP80579 is in this state, it does
not recognize snoops or interrupts. The processor
will only respond to deassertion of CPUSLP_OUT#
or a system reset while in Sleep state. If
CPUSLP_OUT# is deasserted, the processor exits
Sleep state and returns to Stop-Grant state,
restarting its internal clock signals to the bus and
processor core units.
using 4.7KΩ ± 5% resistor if used.
used.
the platform to reset the Firmware Hub. Internal
EP80579 signal that when asserted, resets integer
registers inside the processor without affecting its
internal caches or floating-point registers. The
processor then begins execution at the power-on
Reset vector configured during power-on
configuration. The processor continues to handle
snoop requests during INIT_N assertion. INIT_N is
an asynchronous signal. However, to ensure
recognition of this signal following an Input/Output
Write instruction, it must be valid along with the
TRDY# assertion of the corresponding Input/Output
Write bus transaction.
using 4.7KΩ ± 5% resistor if used.
used.
Order Number: 320068-005US
May 2010
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