Intel EP80579 Manual page 339

Intel
Package length tables are provided for all signals to facilitate the pad to pin matching.
Length formulas should be applied to Memory Down independently. The full geometry
and routing guidelines along with the exact length matching formulas and associated
diagrams are provided in the individual signal group guidelines sections.
DDR2 System Memory Topologies for Memory Down configurations for all signal groups
have a relatively high via usage. This must be considered for the board layout as the
vias and the anti-pads for the vias may restrict power delivery to the memory.
B.6.2 Optimizing Memory Signal Integrity
For all configurations in
• Branch topologies benefit when the length of each branch is as short as possible
and equal to other branches.
• All branch segments should be on the same layer. For example, if there are four L2
segments, then all L2 segments should be the same length and on the same layer.
• If surface mount components are needed (such as a series resistor) for stripline
traces, the signal should return to the same internal layer after completing the
short external layer route.
— Transition layer segment length should be minimized.
• For optimal signal integrity and adequate timing margins, have a continuous
reference return plane, preferably ground, above and below the routing layer.
• Exceptions to the trace width and spacing geometries are allowed in the break-out
region in order to fan out the interconnect pattern. Reduced spacing should be
avoided as much as possible.
B.6.2.1 Stack-Up and Layer Utilization
These guidelines are targeted for platforms that use the stack-up dimensions used by
the Development Board.
While other stack-ups and layer utilization schemes are possible, ensure that the
impedance, velocity, and coupling assumptions used in verifying the signal integrity
and timing of the interface are not compromised.
• The data and data strobe signals should be routed completely on one external
layer, except as required to break out of the EP80579 package.
• When multiple external layers are used, individual byte lanes should be routed as a
group on the same layer.
B.6.2.2 Return Path Continuity for Memory Down Topologies
The DDR2 control signals are ground-referenced on the SDRAM devices. This implies
that the majority of return current will be flowing through the GND pins on the SDRAM
pin and will need to have a contiguous return path back to EP80579. If a power plane is
referenced instead, ensure that a minimum of four AC stitching capacitors are used
near the SDRAM devices' control pins.
B.6.3 Topologies and Routing Guidelines
B.6.3.1 DDR2 Clock Group Signals - DDR_CLK[2:0]/DDR_CLK[2:0]#
The EP80579 clock signal group includes three differential clock pairs per rank. The
following guidelines assume a one-rank design topology. The EP80579 generates and
drives these differential clock signals. Each clock pair is routed to three memory
devices. Table B-27
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Intel EP80579 Integrated Processor Product Line
Platform Design Guide
339
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EP80579 Integrated Processor Product Line—System Memory Interface (Memory Down)
Table B-25, the following recommendations should be followed:
summarizes the clock to memory mapping, Figure B-9 shows the
May 2010
Order Number: 320068-005US