Figure 46. Agp Vddq Generation Example Circuit - Intel 815 Design Manual

AGP/Display Cache Design Guidelines

Figure 46. AGP VDDQ Generation Example Circuit

R1
TYPEDET#
The previous figure demonstrates one way to design the VDDQ voltage regulator. This regulator
is a linear regulator with an external, low-Rds
This regulator converts 3.3V to 1.5V or passes 3.3V, depending on the state of TYPEDET#. If a
linear regulator is used, it must draw power from 3.3V (not 5V) to control thermals
(i.e., 5V regulated down to 1.5V with a linear regulator will dissipate approximately 7 W at 2 A).
Because it must draw power from 3.3V and, in some situations, must simply pass that 3.3V to
VDDQ (when a 3.3V add-in card is placed in the system), the regulator MUST use a low-Rds
FET.
AGP 1.0 ECR #44 modified VDDQ 3.3
3.3 V is 3.168V. Therefore, 68 mV of drop is allowed across the FET at 2 A. This corresponds
min
to a FET with an Rds
How does the regulator switch? The feedback resistor divider is set to 1.5V. When a 1.5V card
is placed in the system, the transistor is Off and the regulator regulates to 1.5V. When a 3.3V card
is placed in the system, the transistor is On, and the feedback will be pulled to ground. When this
happens, the regulator will drive the gate of the FET to nearly 12V. This will turn the FET on and
pass 3.3V – (2 A * Rds
94
+12V
U1
1
SHDN
2
VIN
3
GND
2.2 k
4
1 µF
C1
FB
min
of 34 m .
on
) to VDDQ.
on
+3.3V
C2
LT1575
8
IPOS
5
7
INEG
R2
6
GATE
5
COMP
10 pF
C4
.001 µF
R5
7.5 k - 1%
C5
1.21 k
FET. The source of the FET is connected to 3.3V.
on
to 3.1V. When an ATX power supply is used, the
®
Intel 815 Chipset Platform Design Guide
VDDQ
47 µF
C3 220 µF
R3
301 - 1%
- 1%
R4
AGP_VDDQ_gen_ex_circ
on
R