Ddr2 Point-To-Point Clock Routing Diagram; A-7 Clock Signal Group Routing Guidelines - Intel EP80579 Manual

A.4.5.2 DDR2 Clock Group Signals - DDR_CLK[1:0]/DDR_CLK#[1:0]
The clock signal group for the SODIMM comprises of two differential clock pairs. The
differential clock pairs must be point-to-point routed from the EP80579 to the SODIMM
and must maintain the correct isolation spacing from other signals. Additionally, it is
important to maintain the correct spacing and length matching between the pair to
protect the differential integrity.
Figure A-3
guidelines for the DDR2 differential clocks. Route differential pair signals on the same
layer. No external terminations are required for the clock signals because they are
terminated on the SODIMM.
Figure A-3. DDR2 Point-to-Point Clock Routing Diagram
Table A-7. Clock Signal Group Routing Guidelines (Sheet 1 of 2)
Signal Group
Topology
Reference Plane
Layer Assignment
Characteristic Trace Impedance (Zo)
Nominal Trace Width
®
Intel EP80579 Integrated Processor Product Line
Platform Design Guide
324
®
Intel EP80579 Integrated Processor Product Line—System Memory Interface (SODIMM)
and Table A-7 depict the recommended topology and layout routing
EP80579
EP80579
Pad
Package
Trace
A
A#
L
PKG
Parameter
CLK/CLK#[1:0] - SODIMM
Point-to-Point (Differential)
Ground Referenced
Layers 3/8 (Route Clock group on the same layer)
Single Ended Impedance:
40Ω ±10%
6.5 mils for L3/L8
EP80579 Pin Differential
Breakout
Routing
Routing
B
B#
L
BREAKOUT
Routing Guidelines for SODIMM
SODIMM
Board
C
C#
L
ROUTE
Figure
Figure A-3
Figure A-3
Figure A-3
May 2010
Order Number: 320068-005US