B-31 Ddr2 Address/Command Signal Group Routing Guidelines - Intel EP80579 Manual

Intel
Table B-31. DDR2 Address/Command Signal Group Routing Guidelines
Signal Group
Reference Plane
Layer Assignment
Characteristic Trace Impedance (Zo)
Nominal Trace Width
Nominal Trace Spacing (e2e)
Clearance from other signals
Board Routing Guidelines
Total Trace Length (TTL) = (Lp + L0
+ L1 + L2 + L3 + L4)
Lp
L0
L1
L2
L3
L4
L-ECC
TL1 (Stub to Rtt)
On-Board Termination
Termination Resistor (Rtt)
Routing Length Matching Rules
Inter group signal length matching
(ADD/CMD/CTRL) - to - Clock
B.6.6 DC Bias Signals
The DC bias signals consist of DDR_SLWCRES, DDR_RCOMPX, DDR_CRES[2:0],
DDV_CRES, and DDR_VREF. The routing guidelines for these signals are described in
Section B.6.6.1
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Intel EP80579 Integrated Processor Product Line
Platform Design Guide
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EP80579 Integrated Processor Product Line—System Memory Interface (Memory Down)
Parameter
DDR_MA[14:0], DDR_BA[2:0], DDR_RAS#,
DDR_CAS#, DDR_WE#, DDR_CS[0]#, DDR_CKE[0],
DDR_ODT[0]
Ground Referenced
• Signals must be routed on the same layer
45 Ω ±10%
See Stackup
15 mils
20 mils (min)
Total Trace Length = 2.0 in - 6.0 in
Package Length:
• See the Intel
Microstrip Break-out:
• Trace Length = 0.5 in (max)
Stripline Board Route
• Trace Length = 1.5 in (min) - 4.0 in (max)
Stripline Board Route:
• Trace Length = 0.8 in(max)
Stripline Board Route:
• Trace Length = 0.8 in(max)
Microstrip Break-in
• Trace Length = 0.5 in (max)
ECC Stripline Board Route:
• Trace Length = L2 + L3
Microstrip Route
• Trace Length = 0.4 in (max)
60 Ω ±1%
Match total length of ADD, CMD, and CTRL signals to
within 20 mils of each other.
Match total length of ADD/CMD/CTRL to Clocks to
within 20 mils
• ADD/CMD/CTRL minimum Length = Clock - 0 mils
• ADD/CMD/CTRL maximum Length = Clock +
and Section B.6.6.2.
Routing Guidelines
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EP80579 Integrated Processor Product Line
Datasheet for package length information.
20 mils
Figure
Figure B-27
May 2010
Order Number: 320068-005US